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Groups > linux.kernel > #1590293
| From | Pavel Machek <pavel@ucw.cz> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode |
| Date | 2017-03-01 13:10 +0100 |
| Message-ID | <tgbeW-2ST-7@gated-at.bofh.it> (permalink) |
| References | <t8Aau-Kl-5@gated-at.bofh.it> <t8Irn-5Hm-5@gated-at.bofh.it> <tb4nM-6Eg-1@gated-at.bofh.it> <tcKuB-5Yh-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
[Multipart message — attachments visible in raw view] - view raw
ISP CSI1 module needs all the bits correctly set to work. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Pavel Machek <pavel@ucw.cz> index ca09523..e6584a2 100644 --- a/drivers/media/platform/omap3isp/ispccp2.c +++ b/drivers/media/platform/omap3isp/ispccp2.c @@ -213,14 +236,17 @@ static int ccp2_phyif_config(struct isp_ccp2_device *ccp2, struct isp_device *isp = to_isp_device(ccp2); u32 val; - /* CCP2B mode */ val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) | - ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE; + ISPCCP2_CTRL_MODE; /* Data/strobe physical layer */ BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK, buscfg->phy_layer); + BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT, + ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode); BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK, buscfg->strobe_clk_pol); + BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT, + ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol); isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL); diff --git a/drivers/media/platform/omap3isp/ispreg.h b/drivers/media/platform/omap3isp/ispreg.h index b5ea8da..d084839 100644 --- a/drivers/media/platform/omap3isp/ispreg.h +++ b/drivers/media/platform/omap3isp/ispreg.h @@ -87,6 +87,8 @@ #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1 #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1 #define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2) +#define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1 +#define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2 #define ISPCCP2_CTRL_MODE (1 << 4) #define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9) #define ISPCCP2_CTRL_INV (1 << 10) @@ -94,6 +96,8 @@ #define ISPCCP2_CTRL_INV_SHIFT 10 #define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11) #define ISPCCP2_CTRL_VP_CLK_POL (1 << 12) +#define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1 +#define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15 #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */ #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */ -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [PATCH] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-02-15 10:50 +0100
Re: [PATCH] omap3isp: add support for CSI1 bus Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2017-02-20 02:00 +0100
[PATCH] omap3isp: avoid uninitialized memory Pavel Machek <pavel@ucw.cz> - 2017-02-20 13:10 +0100
Re: [PATCH] omap3isp: avoid uninitialized memory Sakari Ailus <sakari.ailus@iki.fi> - 2017-02-21 12:30 +0100
[media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Pavel Machek <pavel@ucw.cz> - 2017-03-01 13:10 +0100
Re: [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Pavel Machek <pavel@ucw.cz> - 2017-03-03 23:20 +0100
Re: [kbuild-all] [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Ye Xiaolong <xiaolong.ye@intel.com> - 2017-03-10 02:30 +0100
Re: [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Fengguang Wu <lkp@intel.com> - 2017-03-10 03:50 +0100
Re: [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-04 16:20 +0100
Re: [media] omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode Pavel Machek <pavel@ucw.cz> - 2017-03-04 20:50 +0100
Re: [PATCH] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-02 10:10 +0100
[PATCHv2] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-02 11:20 +0100
[PATCH] omap3isp: wait for regulators to come up Pavel Machek <pavel@ucw.cz> - 2017-03-02 13:50 +0100
Re: [PATCH] omap3isp: wait for regulators to come up Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2017-03-02 16:20 +0100
Re: [PATCH] omap3isp: wait for regulators to come up Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-04 16:40 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-02 13:50 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-03 23:20 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-04 14:10 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-04 16:50 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2017-03-04 19:50 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-05 00:00 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-05 15:30 +0100
[PATCH] v4l2-fwnode: Fix clock lane parsing Pavel Machek <pavel@ucw.cz> - 2017-03-06 08:40 +0100
Re: [PATCH] v4l2-fwnode: Fix clock lane parsing Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-11 00:00 +0100
[RFC] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-06 09:00 +0100
Re: [RFC] omap3isp: add support for CSI1 bus Pavel Machek <pavel@ucw.cz> - 2017-03-10 14:50 +0100
Re: [PATCHv2] omap3isp: add support for CSI1 bus Sakari Ailus <sakari.ailus@iki.fi> - 2017-03-02 14:10 +0100
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