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Groups > linux.kernel > #1581610
| From | Tyler Baicar <tbaicar@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH V10 04/10] arm64: exception: handle Synchronous External Abort |
| Date | 2017-02-15 21:00 +0100 |
| Message-ID | <tbdU6-4d3-15@gated-at.bofh.it> (permalink) |
| References | <tbdU5-4d3-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
SEA exceptions are often caused by an uncorrected hardware
error, and are handled when data abort and instruction abort
exception classes have specific values for their Fault Status
Code.
When SEA occurs, before killing the process, report the error
in the kernel logs.
Update fault_info[] with specific SEA faults so that the
new SEA handler is used.
Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org>
Signed-off-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Reviewed-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/esr.h | 1 +
arch/arm64/mm/fault.c | 43 +++++++++++++++++++++++++++++++++----------
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index d14c478..f20c64a 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -83,6 +83,7 @@
#define ESR_ELx_WNR (UL(1) << 6)
/* Shared ISS field definitions for Data/Instruction aborts */
+#define ESR_ELx_FnV (UL(1) << 10)
#define ESR_ELx_EA (UL(1) << 9)
#define ESR_ELx_S1PTW (UL(1) << 7)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 156169c..d178dc0 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -487,6 +487,29 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
return 1;
}
+/*
+ * This abort handler deals with Synchronous External Abort.
+ * It calls notifiers, and then returns "fault".
+ */
+static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
+{
+ struct siginfo info;
+
+ pr_err("Synchronous External Abort: %s (0x%08x) at 0x%016lx\n",
+ fault_name(esr), esr, addr);
+
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = 0;
+ if (esr & ESR_ELx_FnV)
+ info.si_addr = 0;
+ else
+ info.si_addr = (void __user *)addr;
+ arm64_notify_die("", regs, &info, esr);
+
+ return 0;
+}
+
static const struct fault_info {
int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs);
int sig;
@@ -509,22 +532,22 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
- { do_bad, SIGBUS, 0, "synchronous external abort" },
+ { do_sea, SIGBUS, 0, "synchronous external abort" },
{ do_bad, SIGBUS, 0, "unknown 17" },
{ do_bad, SIGBUS, 0, "unknown 18" },
{ do_bad, SIGBUS, 0, "unknown 19" },
- { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous parity error" },
+ { do_sea, SIGBUS, 0, "level 0 (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 1 (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 2 (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 3 (translation table walk)" },
+ { do_sea, SIGBUS, 0, "synchronous parity or ECC error" },
{ do_bad, SIGBUS, 0, "unknown 25" },
{ do_bad, SIGBUS, 0, "unknown 26" },
{ do_bad, SIGBUS, 0, "unknown 27" },
- { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
- { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 0 synchronous parity error (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 1 synchronous parity error (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 2 synchronous parity error (translation table walk)" },
+ { do_sea, SIGBUS, 0, "level 3 synchronous parity error (translation table walk)" },
{ do_bad, SIGBUS, 0, "unknown 32" },
{ do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
{ do_bad, SIGBUS, 0, "unknown 34" },
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
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[PATCH V10 00/10] Add UEFI 2.6 and ACPI 6.1 updates for RAS on ARM64 Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1 Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
Re: [PATCH V10 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1 Ard Biesheuvel <ard.biesheuvel@linaro.org> - 2017-02-16 19:30 +0100
[PATCH V10 03/10] efi: parse ARM processor error Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
Re: [PATCH V10 03/10] efi: parse ARM processor error Ard Biesheuvel <ard.biesheuvel@linaro.org> - 2017-02-16 19:30 +0100
[PATCH V10 09/10] trace, ras: add ARM processor error trace event Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 01/10] acpi: apei: read ack upon ghes record consumption Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 04/10] arm64: exception: handle Synchronous External Abort Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 06/10] acpi: apei: panic OS with fatal error status block Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 05/10] acpi: apei: handle SEA notification type for ARMv8 Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
Re: [PATCH V10 05/10] acpi: apei: handle SEA notification type for ARMv8 Ard Biesheuvel <ard.biesheuvel@linaro.org> - 2017-02-16 19:40 +0100
Re: [PATCH V10 05/10] acpi: apei: handle SEA notification type for ARMv8 "Baicar, Tyler" <tbaicar@codeaurora.org> - 2017-02-21 18:00 +0100
[PATCH V10 08/10] ras: acpi / apei: generate trace event for unrecognized CPER section Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 10/10] arm/arm64: KVM: add guest SEA support Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
[PATCH V10 07/10] efi: print unrecognized CPER section Tyler Baicar <tbaicar@codeaurora.org> - 2017-02-15 21:00 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section Joe Perches <joe@perches.com> - 2017-02-15 21:10 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section "Baicar, Tyler" <tbaicar@codeaurora.org> - 2017-02-15 21:40 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section James Morse <james.morse@arm.com> - 2017-02-21 20:20 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section "Baicar, Tyler" <tbaicar@codeaurora.org> - 2017-02-21 20:40 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section Joe Perches <joe@perches.com> - 2017-02-22 01:40 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section Russell King - ARM Linux <linux@armlinux.org.uk> - 2017-02-22 02:20 +0100
Re: [PATCH V10 07/10] efi: print unrecognized CPER section James Morse <james.morse@arm.com> - 2017-02-22 11:20 +0100
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