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Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm

From Jan Kara <jack@suse.cz>
Newsgroups linux.kernel
Subject Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm
Date 2017-06-14 13:00 +0200
Message-ID <tSebM-48n-27@gated-at.bofh.it> (permalink)
References <tQyRj-6b1-3@gated-at.bofh.it> <tQyRj-6b1-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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On Fri 09-06-17 13:24:29, Dan Williams wrote:
> With all calls to this routine re-directed through the pmem driver, we can kill
> the pmem api indirection. arch_wb_cache_pmem() is now optionally supplied by
> the arch specific asm/pmem.h.  Same as before, pmem flushing is only defined
> for x86_64, but it is straightforward to add other archs in the future.
> 
> Cc: <x86@kernel.org>
> Cc: Jan Kara <jack@suse.cz>
> Cc: Jeff Moyer <jmoyer@redhat.com>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Christoph Hellwig <hch@lst.de>
> Cc: "H. Peter Anvin" <hpa@zytor.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Oliver O'Halloran <oohall@gmail.com>
> Cc: Matthew Wilcox <mawilcox@microsoft.com>
> Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Looks good to me. Just one question below...

> -/**
> - * arch_wb_cache_pmem - write back a cache range with CLWB
> - * @vaddr:	virtual start address
> - * @size:	number of bytes to write back
> - *
> - * Write back a cache range using the CLWB (cache line write back)
> - * instruction. Note that @size is internally rounded up to be cache
> - * line size aligned.
> - */
>  static inline void arch_wb_cache_pmem(void *addr, size_t size)
>  {
> -	u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
> -	unsigned long clflush_mask = x86_clflush_size - 1;
> -	void *vend = addr + size;
> -	void *p;
> -
> -	for (p = (void *)((unsigned long)addr & ~clflush_mask);
> -	     p < vend; p += x86_clflush_size)
> -		clwb(p);
> +	clean_cache_range(addr,size);
>  }

So this will make compilation break on 32-bit x86 as it does not define
clean_cache_range(). Do we somewhere force we are on x86_64 when pmem is
enabled?

								Honza
-- 
Jan Kara <jack@suse.com>
SUSE Labs, CR

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Thread

[PATCH v3 08/14] x86, dax,  libnvdimm: move wb_cache_pmem() to libnvdimm Dan Williams <dan.j.williams@intel.com> - 2017-06-09 22:40 +0200
  [PATCH v4 08/14] x86, dax,  libnvdimm: move wb_cache_pmem() to libnvdimm Dan Williams <dan.j.williams@intel.com> - 2017-06-12 02:40 +0200
  Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to  libnvdimm Jan Kara <jack@suse.cz> - 2017-06-14 13:00 +0200
    Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm Dan Williams <dan.j.williams@intel.com> - 2017-06-14 18:50 +0200
      Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to  libnvdimm Jan Kara <jack@suse.cz> - 2017-06-15 10:20 +0200
  Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to         libnvdimm Christoph Hellwig <hch@lst.de> - 2017-06-18 10:50 +0200
    Re: [PATCH v3 08/14] x86, dax, libnvdimm: move wb_cache_pmem() to libnvdimm Dan Williams <dan.j.williams@intel.com> - 2017-06-19 04:10 +0200

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