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Groups > linux.kernel > #1560000
| From | Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts |
| Date | 2017-01-16 20:20 +0100 |
| Message-ID | <t0kYW-4Ub-17@gated-at.bofh.it> (permalink) |
| References | <t0kvU-4pV-7@gated-at.bofh.it> <t0kvU-4pV-21@gated-at.bofh.it> |
| Organization | Intel Finland Oy |
On Mon, 2017-01-16 at 19:44 +0100, Jan Kiszka wrote:
> When using the a device with edge-triggered interrupts, such as MSIs,
> the interrupt handler has to ensure that there is a point in time
> during
> its execution where all interrupts sources are silent so that a new
> event can trigger a new interrupt again.
>
> This is achieved here by looping over SSSR evaluation. We need to take
> into account that SSCR1 may be changed by the transfer handler, thus
> we
> need to redo the mask calculation, at least regarding the volatile
> interrupt enable bit (TIE).
>
So, more comments/questions below.
>
> sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
>
> - /* Ignore possible writes if we don't need to write */
> - if (!(sccr1_reg & SSCR1_TIE))
> - mask &= ~SSSR_TFS;
> -
> /* Ignore RX timeout interrupt if it is disabled */
> if (!(sccr1_reg & SSCR1_TINTE))
> mask &= ~SSSR_TINT;
>
> - if (!(status & mask))
> - return IRQ_NONE;
> + while (1) {
Can we switch to do-while and move previous block here? Btw, can TINTE
bit be set again during a loop?
> + /* Ignore possible writes if we don't need to write
> */
> + if (!(sccr1_reg & SSCR1_TIE))
> + mask &= ~SSSR_TFS;
>
> - if (!drv_data->master->cur_msg) {
> - handle_bad_msg(drv_data);
> - /* Never fail */
> - return IRQ_HANDLED;
> - }
> + if (!(status & mask))
> + return ret;
> +
> + if (!drv_data->master->cur_msg) {
> + handle_bad_msg(drv_data);
> + /* Never fail */
> + return IRQ_HANDLED;
> + }
> +
> + ret |= drv_data->transfer_handler(drv_data);
So, we might call handler several times. This needs to be commented in
the code why you do so.
>
> - return drv_data->transfer_handler(drv_data);
> + status = pxa2xx_spi_read(drv_data, SSSR);
Would it be possible to get all 1:s from the register
(something/autosuspend just powered off it by timeout?) ?
> + sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
> + }
> }
>
> /*
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
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[PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-16 19:50 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2017-01-16 20:20 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-16 20:50 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-17 20:20 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Robert Jarzmik <robert.jarzmik@free.fr> - 2017-01-17 09:00 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-17 09:20 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jarkko Nikula <jarkko.nikula@linux.intel.com> - 2017-01-17 14:20 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-17 16:00 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Robert Jarzmik <robert.jarzmik@free.fr> - 2017-01-17 09:00 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-17 09:10 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Robert Jarzmik <robert.jarzmik@free.fr> - 2017-01-18 09:30 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-18 10:40 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Mark Brown <broonie@kernel.org> - 2017-01-18 13:50 +0100
Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-19 17:10 +0100
[PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-19 20:40 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2017-01-19 21:10 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Mark Brown <broonie@kernel.org> - 2017-01-20 13:30 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Jan Kiszka <jan.kiszka@siemens.com> - 2017-01-20 16:40 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Mark Brown <broonie@kernel.org> - 2017-01-20 18:40 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Mark Brown <broonie@kernel.org> - 2017-01-19 21:30 +0100
Re: [PATCH v3 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts Robert Jarzmik <robert.jarzmik@free.fr> - 2017-01-20 09:00 +0100
Applied "spi: pxa2xx: Prepare for edge-triggered interrupts" to the spi tree Mark Brown <broonie@kernel.org> - 2017-01-24 19:50 +0100
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