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Groups > linux.kernel > #1500440
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu |
| Date | 2016-10-13 18:40 +0200 |
| Message-ID | <srRcZ-5TH-29@gated-at.bofh.it> (permalink) |
| References | <srLTY-2pk-15@gated-at.bofh.it> |
| Organization | ARM Ltd |
On Thu, 13 Oct 2016 18:57:14 +0800
Cheng Chao <cs.os.kernel@gmail.com> wrote:
> GIC can distribute an interrupt to more than one cpu,
> but now, gic_set_affinity sets only one cpu to handle interrupt.
What makes you think this is a good idea? What purpose does it serves?
I can only see drawbacks to this: You're waking up more than one CPU,
wasting power, adding jitter and clobbering the cache.
I assume you see a benefit to that approach, so can you please spell it
out?
>
> Signed-off-by: Cheng Chao <cs.os.kernel@gmail.com>
> ---
> drivers/irqchip/irq-gic.c | 28 ++++++++++++++++++++++++----
> 1 file changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 58e5b4e..198d33f 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -328,18 +328,38 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
> u32 val, mask, bit;
> unsigned long flags;
> + u32 valid_mask;
>
> - if (!force)
> - cpu = cpumask_any_and(mask_val, cpu_online_mask);
> - else
> + if (!force) {
> + valid_mask = cpumask_bits(mask_val)[0];
> + valid_mask &= cpumask_bits(cpu_online_mask)[0];
> +
> + cpu = cpumask_any((struct cpumask *)&valid_mask);
What is wrong with with cpumask_any_and?
> + } else {
> cpu = cpumask_first(mask_val);
> + }
>
> if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
> return -EINVAL;
>
> gic_lock_irqsave(flags);
> mask = 0xff << shift;
> - bit = gic_cpu_map[cpu] << shift;
> +
> + if (!force) {
> + bit = 0;
> +
> + for_each_cpu(cpu, (struct cpumask *)&valid_mask) {
> + if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
> + break;
Shouldn't that be an error?
> +
> + bit |= gic_cpu_map[cpu];
> + }
> +
> + bit = bit << shift;
> + } else {
> + bit = gic_cpu_map[cpu] << shift;
> + }
> +
> val = readl_relaxed(reg) & ~mask;
> writel_relaxed(val | bit, reg);
> gic_unlock_irqrestore(flags);
Thanks,
M.
--
Jazz is not dead. It just smells funny.
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[PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Cheng Chao <cs.os.kernel@gmail.com> - 2016-10-13 13:00 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Cheng Chao <cs.os.kernel@gmail.com> - 2016-10-13 13:20 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Marc Zyngier <marc.zyngier@arm.com> - 2016-10-13 18:40 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Cheng Chao <cs.os.kernel@gmail.com> - 2016-10-14 04:10 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Marc Zyngier <marc.zyngier@arm.com> - 2016-10-14 19:40 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Cheng Chao <cs.os.kernel@gmail.com> - 2016-10-15 09:30 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Marc Zyngier <marc.zyngier@arm.com> - 2016-10-25 12:10 +0200
Re: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Cheng Chao <cs.os.kernel@gmail.com> - 2016-10-26 04:10 +0200
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