Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1497116

[PATCH v1 0/6] PMC Core driver new features

Show all headers | View raw

This patch series adds few new features to the Intel PMC Core driver
applicable for Skylake & Kabylake SoCs with Sunrise Point LP PCH. These new
features enhance the low power debug capabilities on Intel platforms. These
debug features can be used for platform power optimization. Please refer to
the commit messages of the individual patches and the 7th Generation Intel
Processor Families I/O for U/Y Platforms datasheet for more documentation.

New debug features:

1. PCH IP Power Gating Status
2. ModPhy Core Lanes Power Gating Status
3. ModPhy PLL (Common Lanes) clock Gating Status
4. LTR Ignore feature
5. Support for Kabylake SoC

Rajneesh Bhardwaj (6):
  intel_pmc_core: Fix PWRMBASE mask and mmio reg len
  intel_pmc_core: Add PCH IP Power Gating Status
  intel_pmc_core: ModPhy core lanes pg status
  intel_pmc_core: Add MPHY PLL clock gating status
  intel_pmc_core: Add LTR IGNORE debug feature
  intel_pmc_core: Add KBL CPUID support

 drivers/platform/x86/intel_pmc_core.c | 386 +++++++++++++++++++++++++++++++++-
 drivers/platform/x86/intel_pmc_core.h | 110 +++++++++-
 2 files changed, 490 insertions(+), 6 deletions(-)

-- 
1.9.1

Back to linux.kernel | Previous | Next — Next in thread | Find similar | Unroll thread

Thread

[PATCH v1 0/6] PMC Core driver new features Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> - 2016-10-07 12:40 +0200
  [PATCH v1 1/6] intel_pmc_core: Fix PWRMBASE mask and mmio reg len Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> - 2016-10-07 12:40 +0200
  [PATCH v1 4/6] intel_pmc_core: Add MPHY PLL clock gating status Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> - 2016-10-07 12:40 +0200

csiph-web