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Groups > comp.lang.c++ > #79965
| From | Bonita Montero <Bonita.Montero@gmail.com> |
|---|---|
| Newsgroups | comp.lang.c++ |
| Subject | Re: A single linked list using a futex... |
| Date | 2021-05-26 08:17 +0200 |
| Organization | A noiseless patient Spider |
| Message-ID | <s8kp5j$3pj$1@dont-email.me> (permalink) |
| References | <s8kaa0$i6a$1@gioia.aioe.org> |
I'm too lazy to read your code. > #define CT_L2_ALIGNMENT 128 But this is a false assumption. Except from the Intel Pentium 4 and the IBM POWER's L4-caches (embedded DRAM) there are AFAIK no caches that have 128 byte cacheline size. 128 byte cachelines have been pro- ven to be inefficient below a certain cache-size because the cache- lines become used too partitially as there's a too less reusage-be- haviour of the working-set. Better use this: https://en.cppreference.com/w/cpp/thread/hardware_destructive_interference_size
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A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 19:03 -0700
Re: A single linked list using a futex... Bonita Montero <Bonita.Montero@gmail.com> - 2021-05-26 04:35 +0200
Re: A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 19:42 -0700
Re: A single linked list using a futex... Bonita Montero <Bonita.Montero@gmail.com> - 2021-05-26 04:45 +0200
Re: A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 19:57 -0700
Re: A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 22:59 -0700
Re: A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 22:59 -0700
Re: A single linked list using a futex... Bonita Montero <Bonita.Montero@gmail.com> - 2021-05-26 08:17 +0200
Re: A single linked list using a futex... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2021-05-25 23:21 -0700
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