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Groups > linux.kernel > #1453073
| From | Xing Zheng <zhengxing@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs |
| Date | 2016-08-01 11:40 +0200 |
| Message-ID | <s1hRw-4vm-29@gated-at.bofh.it> (permalink) |
| References | <s1hRw-4vm-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- Changes in v2: None include/dt-bindings/clock/rk3399-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
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[PATCH v2 0/7] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:40 +0200 [PATCH v2 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:40 +0200 [PATCH v2 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:40 +0200 [PATCH v2 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:40 +0200 [PATCH v2 7/7] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng <zhengxing@rock-chips.com> - 2016-08-01 11:50 +0200
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