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Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

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Hi Doug,

On 2016年08月03日 08:49, Doug Anderson wrote:
> Xing,
>
> On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng <zhengxing@rock-chips.com> wrote:
>> From: Elaine Zhang <zhangqing@rock-chips.com>
>>
>> The suggestion that is from IC designer, the correct pll sequence setting
>> should be like these:
>> ----
>>    set pll to slow mode or other plls
>>    set pll down
>>    set pll params
>>    set pll up
>>    wait pll lock status
>>    set pll to normal mode
>> ----
>>
>> Hence, there are potential risks that we need to fix:
>> rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
>> rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old params
> I still don't understand how that groks with the statement in the TRM:
>
>> In most cases the PLL programming can be changed on-the-fly and the PLL will simply slew to the new frequency
> That makes it sound like these PLLs are super great at dynamic updates.
>
>
Well, I will report it to IC & Doc folkers to update the TRM and make it 
clear.

Thanks.

-- 
- Xing Zheng

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[PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq Xing Zheng <zhengxing@rock-chips.com> - 2016-08-02 15:20 +0200
  Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change  pll freq Doug Anderson <dianders@chromium.org> - 2016-08-03 03:00 +0200
    Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change  pll freq Xing Zheng <zhengxing@rock-chips.com> - 2016-08-03 03:30 +0200

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