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Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support

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On Thu, 2016-07-28 at 10:21 -0500, atull wrote:
> > >
> > > This isn't going work if more than one bridge is used.  Each bridge has
> > > its own priv and thus priv->l3_remap_value.  Each bridge's priv will
> > > have just the bit for it's own remap set.  The 2nd bridge to be enabled
> > > will turn off the 1st bridge when it re-write the l3 register.
> > 
> > I can confirm this is exactly what happens with tag
> > "rel_socfpga-4.1.22-ltsi_16.06.02_pr" of socfpga-4.1.22-ltsi branch
> > from altera-opensource/linux-socfpga which includes more or less the
> > code in this patch. If you have 2 bridges (lw-hps2fpga and hps2fpga)
> > you end up with only one of them being visible. Easily spot by logging
> > l3_remap_value being passed to regmap_write()...
> > 
> 
> Anatolij kindly provided a patch for this issue.  I'll push it
> to my github repo when I can.

I still think a better solution would be to allow the syscon driver
manage shared access.  The purpose of syscon is to manage access to a
shared resource from multiple devices.  And regmap already has the
ability to cache a write-only register and allow thread safe access to
modify bits in said register.  The problem is just the pain of trying to
do anything to syscon DT bindings.  Something like "write-only" in the
syscon binding that sets a couple values in the regmap_config is all
that's necessary.

Might as well not use syscon at all and have the bridge driver map the
l3regs itself, since it doesn't really use syscon for anything.

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Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support Andrea Galbusera <gizero@gmail.com> - 2016-07-28 12:30 +0200
  Re: [PATCH v16 6/6] ARM: socfpga: fpga bridge driver support Trent Piepho <tpiepho@kymetacorp.com> - 2016-07-28 22:40 +0200

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