Re: [PATCH 0/6] Intel Secure Guard Extensions

From	Pavel Machek <pavel@ucw.cz>
Newsgroups	linux.kernel
Subject	Re: [PATCH 0/6] Intel Secure Guard Extensions
Date	2016-05-01 11:50 +0200
Message-ID	<rtWaK-7nA-7@gated-at.bofh.it> (permalink)
References	<rtoLM-5gy-11@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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Hi!
On Fri 2016-04-29 23:17:44, Jarkko Sakkinen wrote:
> On Tue, Apr 26, 2016 at 09:00:10PM +0200, Pavel Machek wrote:
> > On Mon 2016-04-25 20:34:07, Jarkko Sakkinen wrote:
> > > The firmware uses PRMRR registers to reserve an area of physical memory
> > > called Enclave Page Cache (EPC). There is a hardware unit in the
> > > processor called Memory Encryption Engine. The MEE encrypts and decrypts
> > > the EPC pages as they enter and leave the processor package.
> > 
> > What are non-evil use cases for this?
> 
> I'm not sure what you mean by non-evil.

Well, that's kind of hard to explain.

> > What are non-evil use cases for this?
> 
> Virtual TPMs for containers/guests would be one such use case.

..but as long as Intel has to sign each piece of software so that it
can use SGX, it is unsuitable for Linux kernel.

Best regards,
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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Re: [PATCH 0/6] Intel Secure Guard Extensions Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> - 2016-04-30 00:10 +0200
  Re: [PATCH 0/6] Intel Secure Guard Extensions Pavel Machek <pavel@ucw.cz> - 2016-05-01 11:50 +0200

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