Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519 soc

From	Stephen Boyd <sboyd@codeaurora.org>
Newsgroups	linux.kernel
Subject	Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519 soc
Date	2016-04-16 02:50 +0200
Message-ID	<romAV-3l3-3@gated-at.bofh.it> (permalink)
References	<riG9k-29W-1@gated-at.bofh.it> <riG9l-29W-43@gated-at.bofh.it> <ro0TM-3bX-13@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On 04/15, Jiancheng Xue wrote:
> Hi,
> 
> On 2016/3/31 16:10, Jiancheng Xue wrote:
> > From: Jiancheng Xue <xuejiancheng@huawei.com>
> > 
> > The CRG(Clock and Reset Generator) block provides clock
> > and reset signals for other modules in hi3519 soc.
> > 
> > Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> > ---
> I hope this patchset can be merged through arch/arm tree
> The dts binding part has been acked by Rob Herring, and
> the reset part has been acked by Philipp Zabel. Could you
> help me to ack this whole clk patch? Please also let me
> know if this patch still have issues. Thank you very much!

Can I merge it through clk tree and make a stable branch to pull
through arm-soc? I assume another patch is coming but it's good
to get clarity before then.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Thread

Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519  soc Jiancheng Xue <xuejiancheng@huawei.com> - 2016-04-15 03:40 +0200
  Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519  soc Stephen Boyd <sboyd@codeaurora.org> - 2016-04-16 02:50 +0200
    Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519  soc Jiancheng Xue <xuejiancheng@huawei.com> - 2016-04-18 05:00 +0200

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