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Re: [PATCH RFC 0/8] mtd: spi-nor: fix support of Quad SPI memories

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On 04/13/2016 07:23 PM, Cyrille Pitchen wrote:
> Hi all,
> 
> this series is RFC but has already been tested on a sama5d2x xplained
> board with the Atmel QSPI controller + Micron n25q128a13:
> compatible = "micron,n25q128a13", "jedec,spi-nor";
> 
> This first 3 patches of the series are stable and have already been
> submitted to linux-mtd. They are required as a base for the later
> patches.
> 
> Support of Micron memories has been implemented as an example, other
> memory entries should be updated as needed in the spi_nor_ids[] table.
> 
> This new way to support Quad SPI memories is inspired by the JEDEC
> SFDP standard. However SFDP tables are not provided by all memories and
> some of them badly implement the standard. Also the standard itself
> can tell whether the memory supports the 2-2-2 mode but doesn't provide
> the procedure to enter/leave this mode as provided for the 4-4-4 mode.
> 
> 
> Please note that some commit messages are missing but a review might be
> really helpfull! :)
> 
> Almost all the actual rework is done in patch 4.

For Altera SoCFPGA , Cadence QSPI NOR controller , Terasic SoCkit board:
Tested-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

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[PATCH RFC 0/8] mtd: spi-nor: fix support of Quad SPI memories Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 2/8] mtd: spi-nor: allow different flash_info entries to share the same JEDEC ID Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 7/8] Documentation: atmel-quadspi: add binding file for Atmel QSPI driver Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 5/8] mtd: m25p80: add support of dual and quad spi protocols to all commands Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 1/8] mtd: spi-nor: add an alternative method to support memory >16MiB Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 3/8] mtd: spi-nor: add entry for Macronix mx25l25673g Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 6/8] mtd: spi-nor: add support for Micron Dual and Quad SPI memories Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
  [PATCH RFC 4/8] mtd: spi-nor: fix support of Dual (x-y-2) and Quad (x-y-4) SPI protocols Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-13 19:30 +0200
    Re: [PATCH RFC 4/8] mtd: spi-nor: fix support of Dual (x-y-2) and  Quad (x-y-4) SPI protocols Marek Vasut <marex@denx.de> - 2016-04-16 00:20 +0200
      Re: [PATCH RFC 4/8] mtd: spi-nor: fix support of Dual (x-y-2) and  Quad (x-y-4) SPI protocols Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-25 14:10 +0200
    Re: [PATCH RFC 4/8] mtd: spi-nor: fix support of Dual (x-y-2) and  Quad (x-y-4) SPI protocols "R, Vignesh" <vigneshr@ti.com> - 2016-04-24 07:10 +0200
      Re: [PATCH RFC 4/8] mtd: spi-nor: fix support of Dual (x-y-2) and  Quad (x-y-4) SPI protocols Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2016-04-25 11:40 +0200
  Re: [PATCH RFC 0/8] mtd: spi-nor: fix support of Quad SPI memories Marek Vasut <marex@denx.de> - 2016-04-16 00:00 +0200

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