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Re: [Xen-devel] [PATCH] xen/events: Mask a moving irq

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On 17/03/16 12:45, Boris Ostrovsky wrote:
> Moving an unmasked irq may result in irq handler being invoked on both
> source and target CPUs.
> 
> With 2-level this can happen as follows:
> 
> On source CPU:
>         evtchn_2l_handle_events() ->
>             generic_handle_irq() ->
>                 handle_edge_irq() ->
>                    eoi_pirq():
>                        irq_move_irq(data);
> 
>                        /***** WE ARE HERE *****/
> 
>                        if (VALID_EVTCHN(evtchn))
>                            clear_evtchn(evtchn);
> 
> If at this moment target processor is handling an unrelated event in
> evtchn_2l_handle_events()'s loop it may pick up our event since target's
> cpu_evtchn_mask claims that this event belongs to it *and* the event is
> unmasked and still pending. At the same time, source CPU will continue
> executing its own handle_edge_irq().
> 
> With FIFO interrupt the scenario is similar: irq_move_irq() may result
> in a EVTCHNOP_unmask hypercall which, in turn, may make the event
> pending on the target CPU.
> 
> We can avoid this situation by moving and clearing the event while
> keeping event masked.

Can you do:

   if (unlikely(irqd_is_setaffinity_pending(data))) {
       masked = test_and_set_mask()

       clear_evtchn()
       irq_move_masked_irq()

       unmask(masked);
   } else
       clear_evtchn()

David

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[PATCH] xen/events: Mask a moving irq Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-03-17 13:50 +0100
  Re: [Xen-devel] [PATCH] xen/events: Mask a moving irq David Vrabel <david.vrabel@citrix.com> - 2016-03-17 17:10 +0100
    Re: [Xen-devel] [PATCH] xen/events: Mask a moving irq Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-03-17 18:00 +0100
      Re: [Xen-devel] [PATCH] xen/events: Mask a moving irq David Vrabel <david.vrabel@citrix.com> - 2016-03-17 18:30 +0100
        Re: [Xen-devel] [PATCH] xen/events: Mask a moving irq Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-03-17 18:50 +0100

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