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Groups > linux.kernel > #1446936

[PATCH 1/4] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable

From Bibby Hsieh <bibby.hsieh@mediatek.com>
Newsgroups linux.kernel
Subject [PATCH 1/4] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable
Date 2016-07-20 06:10 +0200
Message-ID <rWQZz-4St-9@gated-at.bofh.it> (permalink)
References <rWQZz-4St-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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From: Junzhi Zhao <junzhi.zhao@mediatek.com>

The mtk_hdmi_send_infoframe have to
be run after PLL and PIXEL clock of HDMI enable.
Make sure that HDMI inforframes can be sent
successfully.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c |   19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index ba812ef..d8609f5 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
 	phy_power_on(hdmi->phy);
 	mtk_hdmi_aud_output_config(hdmi, mode);
 
-	mtk_hdmi_setup_audio_infoframe(hdmi);
-	mtk_hdmi_setup_avi_infoframe(hdmi, mode);
-	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
-	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
-		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
-
 	mtk_hdmi_hw_vid_black(hdmi, false);
 	mtk_hdmi_hw_aud_unmute(hdmi);
 	mtk_hdmi_hw_send_av_unmute(hdmi);
@@ -1401,14 +1395,25 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
 	hdmi->powered = true;
 }
 
+static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
+				    struct drm_display_mode *mode)
+{
+	mtk_hdmi_setup_audio_infoframe(hdmi);
+	mtk_hdmi_setup_avi_infoframe(hdmi, mode);
+	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
+	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
+		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
+}
+
 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
 {
 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
 
+	phy_power_on(hdmi->phy);
 	mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
-	phy_power_on(hdmi->phy);
+	mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
 
 	hdmi->enabled = true;
 }
-- 
1.7.9.5

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Thread

[PATCH 0/4] MT8173 HDMI 4K support Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-20 06:10 +0200
  [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when resolution is 4K Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-20 06:10 +0200
    Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K CK Hu <ck.hu@mediatek.com> - 2016-07-20 10:00 +0200
      Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-25 08:30 +0200
        Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K CK Hu <ck.hu@mediatek.com> - 2016-07-25 09:00 +0200
          Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-25 10:40 +0200
    Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K Philipp Zabel <p.zabel@pengutronix.de> - 2016-07-20 11:50 +0200
      Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when  resolution is 4K Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-25 08:30 +0200
  [PATCH 1/4] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-20 06:10 +0200
  [PATCH 2/4] drm/mediatek: enhance the HDMI driving current Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-20 06:10 +0200
    Re: [PATCH 2/4] drm/mediatek: enhance the HDMI driving current CK Hu <ck.hu@mediatek.com> - 2016-07-20 09:20 +0200
      Re: [PATCH 2/4] drm/mediatek: enhance the HDMI driving current Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-25 08:20 +0200
  [PATCH 4/4] drm/mediatek: adjust VENCPLL clock for 4K HDMI output Bibby Hsieh <bibby.hsieh@mediatek.com> - 2016-07-20 06:10 +0200
    Re: [PATCH 4/4] drm/mediatek: adjust VENCPLL clock for 4K HDMI  output Philipp Zabel <p.zabel@pengutronix.de> - 2016-07-20 12:00 +0200

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