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Groups > linux.kernel > #1420253
| From | Dong Aisheng <dongas86@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents |
| Date | 2016-06-12 14:00 +0200 |
| Message-ID | <rJcdA-8bT-23@gated-at.bofh.it> (permalink) |
| References | <rI2SZ-3kN-9@gated-at.bofh.it> <rJc3U-88s-19@gated-at.bofh.it> <rJc3U-88s-17@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote: > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote: > > pllx_bypass_src mux shouldn't be the parent of pllx clock > > since it's only valid when when pllx BYPASS bit is set. > > Thus it is actually one parent of pllx_bypass only. > > > > Instead, pllx parent should be fixed to osc according to > > reference manual. > > Other plls have the same issue. > > > > e.g. before fix, the pll tree is: > > osc 6 6 24000000 0 0 > > pll1_bypass_src 0 0 24000000 0 0 > > pll1 0 0 792000000 0 0 > > pll1_bypass 0 0 792000000 0 0 > > pll1_sys 0 0 792000000 0 0 > > > > After the fix, it's: > > osc 6 6 24000000 0 0 > > pll1 0 0 792000000 0 0 > > pll1_bypass 0 0 792000000 0 0 > > pll1_sys 0 0 792000000 0 0 > > > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > > I squashed 7 ~ 11 into one patch and applied it, thanks. > I'm fine. Thanks Regards Dong Aisheng > Shawn > -- > To unsubscribe from this list: send the line "unsubscribe linux-clk" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
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Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Shawn Guo <shawnguo@kernel.org> - 2016-06-12 13:50 +0200
Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng <dongas86@gmail.com> - 2016-06-12 14:00 +0200
Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng <dongas86@gmail.com> - 2016-06-12 14:30 +0200
Re: [PATCH 07/11] clk: imx6ul: fix pll clock parents Shawn Guo <shawnguo@kernel.org> - 2016-06-12 15:30 +0200
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