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Groups > linux.kernel > #1406022
| From | Catalin Marinas <catalin.marinas@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu |
| Date | 2016-05-24 12:00 +0200 |
| Message-ID | <rChi3-1AN-47@gated-at.bofh.it> (permalink) |
| References | <rBN0C-7Wt-5@gated-at.bofh.it> <rBN0C-7Wt-13@gated-at.bofh.it> <rBVAR-4HP-11@gated-at.bofh.it> <rBYfo-6sj-35@gated-at.bofh.it> <rCaqe-5CJ-25@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Tue, May 24, 2016 at 10:31:17AM +0800, Shunqian Zheng wrote:
> On 2016年05月23日 21:35, Catalin Marinas wrote:
> >On Mon, May 23, 2016 at 11:44:14AM +0100, Robin Murphy wrote:
> >>On 23/05/16 02:37, Shunqian Zheng wrote:
> >>>From: Simon <xxm@rock-chips.com>
> >>>
> >>>Signed-off-by: Simon <xxm@rock-chips.com>
> >>>---
> >>> drivers/iommu/rockchip-iommu.c | 4 ++++
> >>> 1 file changed, 4 insertions(+)
> >>>
> >>>diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
> >>>index 043d18c..1741b65 100644
> >>>--- a/drivers/iommu/rockchip-iommu.c
> >>>+++ b/drivers/iommu/rockchip-iommu.c
> >>>@@ -95,12 +95,16 @@ struct rk_iommu {
> >>>
> >>> static inline void rk_table_flush(u32 *va, unsigned int count)
> >>> {
> >>>+#if defined(CONFIG_ARM)
> >>> phys_addr_t pa_start = virt_to_phys(va);
> >>> phys_addr_t pa_end = virt_to_phys(va + count);
> >>> size_t size = pa_end - pa_start;
> >>>
> >>> __cpuc_flush_dcache_area(va, size);
> >>> outer_flush_range(pa_start, pa_end);
> >>>+#elif defined(CONFIG_ARM64)
> >>>+ __dma_flush_range(va, va + count);
> >>>+#endif
> >>Ugh, please don't use arch-private cache maintenance functions directly from
> >>a driver. Allocating/mapping page tables to be read by the IOMMU is still
> >>DMA, so using the DMA APIs is the correct way to manage them, *especially*
> >>if it needs to work across multiple architectures.
>
> It's easier for us if changing the __dma_flush_range() to
> __flush_dcache_area() is acceptable here?
It's not really acceptable for arm64, nor for arm32. Please fix this
driver in a similar way to commit e3c971960fd4 ("iommu/tegra-smmu:
Convert to use DMA API").
The only place where we allowed __flush_dcache_area() is in the GICv3
driver and that's because it hasn't been wired as a platform device
(yet).
--
Catalin
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[PATCH 0/5] iommu/rockchip: fix bugs; enable iommu for ARM64 Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-23 03:40 +0200
[PATCH 5/5] iommu/rockchip: enable rockchip iommu on ARM64 platform Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-23 03:40 +0200
[PATCH 2/5] iommu/rockchip: add map_sg callback for rk_iommu_ops Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-23 03:40 +0200
[PATCH 3/5] iommu/rockchip: add sanity check for virtual device Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-23 03:40 +0200
[PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-23 03:40 +0200
Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Robin Murphy <robin.murphy@arm.com> - 2016-05-23 12:50 +0200
Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Catalin Marinas <catalin.marinas@arm.com> - 2016-05-23 15:40 +0200
Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Shunqian Zheng <zhengsq@rock-chips.com> - 2016-05-24 04:40 +0200
Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Catalin Marinas <catalin.marinas@arm.com> - 2016-05-24 12:00 +0200
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