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Re: IIGS - Linear mapping?

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Thanks for your explanation of the linearized superhires mode.

The following two things are now clear to me:

1) the 6000-9fff segments of banks E0 and E1 are swapped. They do not reside in physical memory banks A and B, but in B and A  (as explained in TN32)

2) the linearization bit interleaves the bytes of the segments E1/2000-5fff and E1/6000-9fff

This means that when the linearization bit is on, the video hardware can access 16 successive bits of the linearized video buffer in a single read cycle.
For instance, the two bytes E1/2000-2001  are located in B/2000 and A/6000. Although they do not appear at the same address, the VGC produces two signals,
FLIP6 and FLIP7, that can swap the high bits of the A bank addresses. These can handle all the address discrepancies.

If we assume that the video hardware only makes one memory access during the first half of the 1Mhz clock cycle, then we have a problem because
we need 32 bits of video data per microsecond to produce the superhires video. Your explanation using the four memory chips is not good
enough because each of them (TMS4464, 150ns) only generate 4 bits. Together the four chips can only produce 16 bits per read cycle.

At this point I conjecture that the VGC in fact makes two memory accesses during that time, using the 4464 fast page mode
where one sets the row address only once, but get data for multiple column addresses.  To get the data, one needs to wait
at least 150ns after asserting RAS and 120ns after asserting CAS. So the following could barely work:


14M cycle
---------
 0   load video address column on the 4464 multiplexed bus RA0-RA7
 1   assert RAS
 2   load first video address row on RA0-RA7
 3   assert CAS
 4   maintain CAS
 5   read 16 bits of video data, deassert CAS, deassert RAS
 6   load second video address row on RA0-RA7
 7   assert CAS
 8   maintain CAS
 9   read 16 nore bits of video data, deassert CAS, deassert RAS
10   load cpu address column on RA0-RA7. 
11   assert CAS 
12   maintain CAS
13   read 8 bits of cpu data, deassert CAS, deassert RAS


What I do not like in this hypothesis is the fact that according to the schematics, the RAS and CAS signals are generated by the MEGA2, not the VGC.  This would mean that the MEGA2 contains a GS-specific circuitry. This is not completely implausible because it probably also contains the circuitry that swaps the banks 6000-9fff and the one that interleaves E1/2000-5fff and E1/6000-9fff. I just do not see where else this could be realized.

Anyway, this is remarkably complex.
 

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IIGS - Linear mapping? paul.s.macmillan@gmail.com - 2018-11-06 11:11 -0800
  Re: IIGS - Linear mapping? James Davis <JPD.Enterprises@outlook.com> - 2018-11-07 00:06 -0800
    Re: IIGS - Linear mapping? kegs@provalid.com (Kent Dickey) - 2018-11-07 08:23 -0600
      Re: IIGS - Linear mapping? John Brooks <jbrooks@blueshiftinc.com> - 2018-11-07 08:35 -0800
        Re: IIGS - Linear mapping? kegs@provalid.com (Kent Dickey) - 2018-11-07 23:29 -0600
          Re: IIGS - Linear mapping? John Brooks <jbrooks@blueshiftinc.com> - 2018-11-08 15:14 -0800
            Re: IIGS - Linear mapping? Dagen Brock <dagenbrock@gmail.com> - 2018-11-09 02:03 -0800
              Re: IIGS - Linear mapping? John Brooks <jbrooks@blueshiftinc.com> - 2018-11-09 14:53 -0800
            Re: IIGS - Linear mapping?  <leonb@novabbs.i2p> - 2020-01-24 22:07 +0000
            Re: IIGS - Linear mapping?  <leonb@novabbs.i2p> - 2020-01-24 22:29 +0000
              Re: IIGS - Linear mapping? Antoine Vignau <antoine.vignau@laposte.net> - 2020-01-24 20:15 -0800

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