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Groups > linux.kernel > #1245176
| From | Josh Cartwright <joshc@eso.teric.us> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller |
| Date | 2015-10-13 00:00 +0200 |
| Message-ID | <qiTip-3jf-1@gated-at.bofh.it> (permalink) |
| References | (3 earlier) <qg7rA-7BU-5@gated-at.bofh.it> <qgAMW-7L3-17@gated-at.bofh.it> <qgJ3R-2UE-39@gated-at.bofh.it> <qgJQe-44b-3@gated-at.bofh.it> <qgNK9-1fB-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
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On Wed, Oct 07, 2015 at 03:33:50AM +0000, Anup Patel wrote:
> From: Florian Fainelli [mailto:f.fainelli@gmail.com]
> > On 06/10/15 15:25, Scott Branden wrote:
[..]
> > Then instead of adding a "reset flag" to Device Tree, another approach could be
> > to put the desired or currently configured exhaustive list of NAND timings in
> > Device Tree, and based on that you could have this:
> >
> > - the NAND controller driver finds that these timings match the current
> > configuration, you are good to go
> >
> > - the NAND controller drivers finds a difference in how current timings are
> > configured vs. desired timings, and issues a controller reset, prior to applying
> > new timing configuration
>
> To add to this ...
>
> The mechanism to reset is BRCM NAND controller is SOC specific so the
> SoC independent BRCM NAND driver (i.e. brcmnand.c) does not know how
> to reset the NAND controller.
>
> For iProc SoC family, the NAND controller reset is through IDM register
> space which is only iomap'ed by iproc_nand.c.
>
> We might end-up having one more SoC specific callback which will be
> Provided by iproc_nand.c to brcmnand.c.
Not that I'm familiar with these SoCs, but I did want to chime in and
make sure you are aware of the existing reset_controller_dev
abstraction, which is intended to solve exactly this problem. Including
a reset_control_get_optional() that might fit your use case. See
include/linux/reset{,-controller}.h.
Josh
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Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Brian Norris <computersforpeace@gmail.com> - 2015-10-06 15:50 +0200
Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Scott Branden <sbranden@broadcom.com> - 2015-10-07 00:40 +0200
Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Florian Fainelli <f.fainelli@gmail.com> - 2015-10-07 01:30 +0200
RE: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Anup Patel <anup.patel@broadcom.com> - 2015-10-07 05:40 +0200
Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Brian Norris <computersforpeace@gmail.com> - 2015-10-12 23:30 +0200
RE: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Anup Patel <anup.patel@broadcom.com> - 2015-10-16 08:50 +0200
Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Josh Cartwright <joshc@eso.teric.us> - 2015-10-13 00:00 +0200
Re: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Florian Fainelli <f.fainelli@gmail.com> - 2015-10-13 19:40 +0200
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