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Groups > linux.kernel > #1244793
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY |
| Date | 2015-10-12 17:10 +0200 |
| Message-ID | <qiMTD-2Aw-7@gated-at.bofh.it> (permalink) |
| References | <qi4pA-54b-13@gated-at.bofh.it> <qi4IY-5qN-29@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
Add phy driver for the Rockchip DisplayPort PHY module. This is required
to get DisplayPort working in Rockchip SoCs.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None
> Changes in v5:
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> the exist "grf" syscon already. And rename the example DT node from
> "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
> struct" to "static const struct". And correct the input paramters of
> devm_phy_create() interfaces. (Heiko)
>
> Changes in v4:
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
> function, move those code to probe() method. And remove driver .owner
> number. (Kishon)
>
> Changes in v3:
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
> power control. (Heiko)
>
> Changes in v2: None
>
> drivers/phy/Kconfig | 7 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 159 insertions(+)
> create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> + tristate "Rockchip Display Port PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip Display Port PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..3a2ac120
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,151 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12 0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON 0
> +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
> +
> +struct rockchip_dp_phy {
> + struct device *dev;
> + struct regmap *grf;
> + struct clk *phy_24m;
> +};
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> + int ret;
> +
> + if (enable) {
> + ret = clk_prepare_enable(dp->phy_24m);
> + if (ret < 0) {
> + dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> + return ret;
> + }
> +
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_PHY_SIDDQ_WRITE_EN |
> + GRF_EDP_PHY_SIDDQ_ON);
> + } else {
> + clk_disable_unprepare(dp->phy_24m);
should clk_disable come after regmap_write? It'll be symmetric to enable?
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_PHY_SIDDQ_WRITE_EN |
> + GRF_EDP_PHY_SIDDQ_OFF);
Is this syscon register used only by Display Port PHY? Better to use
regmap_update API?
Thanks
Kishon
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Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH v6 0/17] Add Analogix Core Display Port Driver Yakir Yang <ykk@rock-chips.com> - 2015-10-10 17:40 +0200
[PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang <ykk@rock-chips.com> - 2015-10-10 17:40 +0200
[PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang <ykk@rock-chips.com> - 2015-10-10 17:50 +0200
[PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang <ykk@rock-chips.com> - 2015-10-10 17:50 +0200
[PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-10 17:50 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-12 02:40 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-12 03:00 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-12 04:50 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-12 06:00 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-12 06:10 +0200
Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-12 06:20 +0200
[PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:00 +0200
[PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:00 +0200
[PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:00 +0200
[PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:00 +0200
Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Kishon Vijay Abraham I <kishon@ti.com> - 2015-10-12 17:10 +0200
Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Heiko Stübner <heiko@sntech.de> - 2015-10-12 18:20 +0200
Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-10-13 03:30 +0200
[PATCH v6 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy Kishon Vijay Abraham I <kishon@ti.com> - 2015-10-13 00:30 +0200
Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang <ykk@rock-chips.com> - 2015-10-13 03:30 +0200
[PATCH v6 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v6 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang <ykk@rock-chips.com> - 2015-10-10 18:10 +0200
[PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-12 06:40 +0200
Re: [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-12 09:00 +0200
Re: [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang <ykk@rock-chips.com> - 2015-10-12 09:30 +0200
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