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Groups > linux.kernel > #1238481

[PATCH 1/6] arm64: dts: Add L2-cache DT node for NS2

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Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Sandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 3c92d92..f759175 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -50,6 +50,7 @@
 			reg = <0 0>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0x84b00000>;
+			next-level-cache = <&CLUSTER0_L2>;
 		};
 
 		cpu@1 {
@@ -58,6 +59,7 @@
 			reg = <0 1>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0x84b00000>;
+			next-level-cache = <&CLUSTER0_L2>;
 		};
 
 		cpu@2 {
@@ -66,6 +68,7 @@
 			reg = <0 2>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0x84b00000>;
+			next-level-cache = <&CLUSTER0_L2>;
 		};
 
 		cpu@3 {
@@ -74,6 +77,11 @@
 			reg = <0 3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0 0x84b00000>;
+			next-level-cache = <&CLUSTER0_L2>;
+		};
+
+		CLUSTER0_L2: l2-cache@000 {
+			compatible = "cache";
 		};
 	};
 
-- 
1.9.1

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[PATCH 0/6] arm64: Simple additions to NS2 DT Anup Patel <anup.patel@broadcom.com> - 2015-10-02 20:00 +0200
  [PATCH 1/6] arm64: dts: Add L2-cache DT node for NS2 Anup Patel <anup.patel@broadcom.com> - 2015-10-02 20:00 +0200
  [PATCH 4/6] arm64: dts: Add ARM PMUv3 DT node in NS2 DT Anup Patel <anup.patel@broadcom.com> - 2015-10-02 20:00 +0200
  [PATCH 2/6] arm64: dts: Add SMMU DT node for NS2 Anup Patel <anup.patel@broadcom.com> - 2015-10-02 20:00 +0200
  [PATCH 6/6] arm64: dts: Add I2C nodes for NS2 Anup Patel <anup.patel@broadcom.com> - 2015-10-02 20:00 +0200

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