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[PATCH] PCI: Add cavium acs pci quirk

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Cavium devices matching this quirk do not perform
peer-to-peer with other functions, allowing masking out
these bits as if they were unimplemented in the ACS capability.

Acked-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Signed-off-by: Manish Jaggi <mjaggi@caviumnetworks.com>
---
 drivers/pci/quirks.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 7e32730..a300fa6 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3814,6 +3814,19 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
 #endif
 }

+static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+{
+	/*
+	 * Cavium devices matching this quirk do not perform
+	 * peer-to-peer with other functions, allowing masking out
+	 * these bits as if they were unimplemented in the ACS capability.
+	 */
+	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
+		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
+
+	return acs_flags ? 0 : 1;
+}
+
 /*
  * Many Intel PCH root ports do provide ACS-like features to disable peer
  * transactions and validate bus numbers in requests, but do not provide an
@@ -3966,6 +3979,8 @@ static const struct pci_dev_acs_enabled {
 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
 	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
 	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
+	/* Cavium ThunderX */
+	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
 	{ 0 }
 };

-- 
1.9.1

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[PATCH] PCI: Add cavium acs pci quirk Manish Jaggi <mjaggi@caviumnetworks.com> - 2016-01-29 22:40 +0100
  Re: [PATCH] PCI: Add cavium acs pci quirk Bjorn Helgaas <helgaas@kernel.org> - 2016-02-05 00:20 +0100

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