Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value

From	Herbert Xu <herbert@gondor.apana.org.au>
Newsgroups	linux.kernel
Subject	Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value
Date	2015-12-17 09:50 +0100
Message-ID	<qGCq6-5pv-1@gated-at.bofh.it> (permalink)
References	<qFdap-7L6-5@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Sun, Dec 13, 2015 at 03:30:41AM -0800, Haren Myneni wrote:
> 
> NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
> nothing to do with NX request. Since this bit can be set with other
> valuable return status, mast this bit.
> 
> One of other bits (INITIATED, BUSY or REJECTED) will be returned for
> any given NX request.
> 
> Signed-off-by: Haren Myneni <haren@us.ibm.com>

Patch applied.  Thanks.
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[PATCH] crypto/nx842: Mask XERS0 bit in return value Haren Myneni <haren@linux.vnet.ibm.com> - 2015-12-13 12:40 +0100
  Re: [PATCH] crypto/nx842: Mask XERS0 bit in return value Herbert Xu <herbert@gondor.apana.org.au> - 2015-12-17 09:50 +0100

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