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Groups > linux.kernel > #1205511
| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk |
| Date | 2015-08-12 02:00 +0200 |
| Message-ID | <pWrCx-3Fa-5@gated-at.bofh.it> (permalink) |
| References | <pWrCx-3Fa-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 07/24, dinguyen@opensource.altera.com wrote: > From: Dinh Nguyen <dinguyen@opensource.altera.com> > > The debug base clock can be bypassed from the main PLL to the OSC1 clock. > The bypass register is the staysoc1(0x10) register that is in the clock > manager. > > This patch adds the option to get the correct parent for the debug base > clock. > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk Stephen Boyd <sboyd@codeaurora.org> - 2015-08-12 02:00 +0200
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