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[PATCH v4 3/7] clk: mediatek: mt8173: Fix enabling of critical clocks

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From: Sascha Hauer <s.hauer@pengutronix.de>

On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical clocks end up being
unused and get disabled later.

On MT8173, for example, it is the CLK_TOP clocks that have CLK_APMIXED
PLLs as their parents, so we cannot enable the CLK_TOP critical clocks
until the CLK_APMIXED clocks have all been registered.

To find a place where all parents are registered we try each time
after we've registered some clocks if all known providers are present
now and only then we enable the critical clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 50b3266..a72ce82 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -699,6 +699,22 @@ static const struct mtk_composite peri_clks[] __initconst = {
 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static struct clk_onecell_data *mt8173_top_clk_data;
+static struct clk_onecell_data *mt8173_pll_clk_data;
+
+static void __init mtk_clk_enable_critical(void)
+{
+	if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
+		return;
+
+	clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
+	clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
+	clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
+	clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
+	clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
+	clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
+}
+
 static void __init mtk_topckgen_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
@@ -711,19 +727,19 @@ static void __init mtk_topckgen_init(struct device_node *node)
 		return;
 	}
 
-	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+	mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 
 	mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 			&mt8173_clk_lock, clk_data);
 
-	clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]);
-
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
+
+	mtk_clk_enable_critical();
 }
 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
 
@@ -817,13 +833,13 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
 
-	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+	mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
 	if (!clk_data)
 		return;
 
 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 
-	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
+	mtk_clk_enable_critical();
 }
 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
 		mtk_apmixedsys_init);
-- 
1.8.1.1.dirty

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Thread

[PATCH v4 0/7] Add Mediatek MT8173 subsystem clocks support James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
  [PATCH v4 6/7] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
    Re: [PATCH v4 6/7] clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS Daniel Kurtz <djkurtz@chromium.org> - 2015-07-24 13:30 +0200
  [PATCH v4 5/7] clk: mediatek: Add subsystem clocks of MT8173 James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
    Re: [PATCH v4 5/7] clk: mediatek: Add subsystem clocks of MT8173 Daniel Kurtz <djkurtz@chromium.org> - 2015-07-24 13:20 +0200
  [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC. James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
    Re: [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for  Mediatek SoC. Daniel Kurtz <djkurtz@chromium.org> - 2015-07-24 13:40 +0200
  [PATCH v4 3/7] clk: mediatek: mt8173: Fix enabling of critical clocks James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
  [PATCH v4 4/7] dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
  [PATCH v4 2/7] clk: mediatek: Fix rate and dependency of MT8173 clocks James Liao <jamesjj.liao@mediatek.com> - 2015-07-24 05:10 +0200
    Re: [PATCH v4 2/7] clk: mediatek: Fix rate and dependency of MT8173 clocks Daniel Kurtz <djkurtz@chromium.org> - 2015-07-24 13:20 +0200

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