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Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support

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On Fri, Jul 17, 2015 at 01:11:41PM +0100, Mark Rutland wrote:
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> > index b9826a9..651a86d 100644
> > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> > @@ -1586,6 +1586,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
> >  	if (!x86_pmu.late_ack)
> >  		apic_write(APIC_LVTPC, APIC_DM_NMI);
> >  	__intel_pmu_disable_all();
> > +	if (cpuc->core_misc_active_mask)
> > +		intel_core_misc_pmu_disable();
> 
> Huh? Free running counters have nothing to do with the PMU interrupt;
> there's nothing they can do to trigger it. This feels very hacky.
> 
> If this is necessary, surely it should live in __intel_pmu_disable_all?
> 
> [...]

Yeah this is crazy. It should not live in the regular PMU at all, not be
Intel specific.
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Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support Mark Rutland <mark.rutland@arm.com> - 2015-07-17 14:20 +0200
  Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support Peter Zijlstra <peterz@infradead.org> - 2015-07-17 15:50 +0200
    Re: [PATCH 2/9] perf/x86: core_misc PMU disable and enable support Peter Zijlstra <peterz@infradead.org> - 2015-07-17 16:00 +0200

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