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Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of some atomic operations

From Will Deacon <will.deacon@arm.com>
Newsgroups linux.kernel
Subject Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of some atomic operations
Date 2015-07-14 18:00 +0200
Message-ID <pMaMG-4Md-25@gated-at.bofh.it> (permalink)
References (4 earlier) <pM66l-189-5@gated-at.bofh.it> <pM6g3-1qz-25@gated-at.bofh.it> <pM6zo-1xb-15@gated-at.bofh.it> <pM6J3-1AF-9@gated-at.bofh.it> <pM6J4-1AF-21@gated-at.bofh.it>
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On Tue, Jul 14, 2015 at 12:38:01PM +0100, Peter Zijlstra wrote:
> On Tue, Jul 14, 2015 at 12:31:47PM +0100, Will Deacon wrote:
> > #ifndef atomic_add
> > #define atomic_add(args...)	(void)atomic_add_return_relaxed(args);
> > 
> > It would mean a new architecture only has to define a barrier instruction
> > and a handful of relaxed atomics for a bare-minimum atomic.h avoiding
> > spinlocks.
> 
> Look at include/asm-generic/atomic.h, all you need is a cmpxchg().
> 
> We could easily change that to be cmpxchg_relaxed() and a few barriers.

Ok, I'll leave that part for now and implement your original suggestion
as a starting point.

Will
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[PATCH 1/5] atomics: add acquire/release/relaxed variants of some atomic operations Will Deacon <will.deacon@arm.com> - 2015-07-13 14:40 +0200
  Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of  some atomic operations Will Deacon <will.deacon@arm.com> - 2015-07-14 18:00 +0200

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