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Re: [alsa-devel][PATCH] ASoC: wm8960: update pll and clock setting function

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On Mon, Jun 29, 2015 at 10:44:12AM +0100, Charles Keepax wrote:
> On Fri, Jun 26, 2015 at 07:09:22PM +0800, Zidan Wang wrote:
> > When using snd_soc_dai_set_pll to set pll in machine driver, we
> > should set pll in and pll out freq and ensure 5 < PLLN < 13,
> > otherwise set pll will be failed. In order to support more
> > formats and sample rates for a certain MCLK, if snd_soc_dai_set_pll
> > failed, it will calculate a available pll out freq and set the pll
> > again.
> > 
> > Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
> > ---
> 
> I think this need a little more explaination on how this is
> expected to work. From looking at the code what it looks like
> what happens is you can set a PLL frequency through set_pll but
> then if that frequency doesn't support the sample rate requested
> through hw_params it will be changed. This makes me a little
> nervous, as something explicitly requested is being overwritten
> automatically.
> 
From RM, we should ensure 5 < PLLN < 13. When i using snd_soc_dai_set_pll
to set pll frequency, it's hard for me to get a common pll out frequency.
Sometimes, when codec MCLK or sample rate changed, the pll out frequency
also should be changed, otherwise set_pll function will be failed.

I made it to auto select pll frequency when snd_soc_dai_set_pll failed, so that
it can support more sample rate, and don't need to set different pll out
frequency for different sample rate and different MCLK.

> Would it perhaps be better to allow the auto selection of the
> PLL frequency only when things haven't been manually set, or
> provide some setting that indicates auto mode?
> 
> Thanks,
> Charles
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Re: [alsa-devel][PATCH] ASoC: wm8960: update pll and clock setting  function Zidan Wang <zidan.wang@freescale.com> - 2015-06-30 12:10 +0200
  Re: [alsa-devel][PATCH] ASoC: wm8960: update pll and clock setting  function Charles Keepax <ckeepax@opensource.wolfsonmicro.com> - 2015-06-30 12:50 +0200

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