Groups > sci.electronics.design > #446912

Re: USB cabling constraints

From	"Tim Williams" <tiwill@seventransistorlabs.com>
Newsgroups	sci.electronics.design
Subject	Re: USB cabling constraints
Date	2017-02-08 17:49 -0600
Organization	A noiseless patient Spider
Message-ID	<o7gana$mc2$1@dont-email.me> (permalink)
References	<o7cpr0$nno$1@dont-email.me> <o7dqs5$mg3$1@dont-email.me> <o7e3iu$3k3$1@dont-email.me>

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"Don Y" <blockedofcourse@foo.invalid> wrote in message 
news:o7e3iu$3k3$1@dont-email.me...
> But, he can produce something that is total shit.  That falls apart during
> "normal" (what's that?) use.  Or, whose performance degrades quickly
> (shields opening up from flexure).  Or, outright failures without being
> unduly stressed (connections opening/wires fraying from handling).

Standards for all these things exist, along with the means to perform the 
tests.  Example: flexure test, consisting of wobbling the cable back and 
forth (do a test at the connector end, too, to see the efficacy of the 
strain relief and braid-to-housing join), for a suitable bend radius and 
number of cycles.  Qualification consists of DC checks (resistance per 
conductor, no shorts between wires), and perhaps a nice RF spot-check too 
(e.g., impedance within tolerance, shield attenuation >60dB, etc.).

I don't know offhand what is recommended, but I expect the USB standard has 
some preferences; if not (or, if not sufficient for your purposes), you can 
surely find better specs, all the way up to mil spec (which is free, also!), 
if you like. :)

Keep in mind that stacking specs will likely give you a higher cost.  You 
can just as well pass that off as in-house quality checks (even better! --  
but more expensive over time), or as qualification testing from a few 
different suppliers and sticking with one (presumably doing spot checks 
every so often to determine if they've cheaped their product on you, and 
it's time to search again).

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com

Thread

USB cabling constraints Don Y <blockedofcourse@foo.invalid> - 2017-02-07 08:43 -0700
  Re: USB cabling constraints amdx <nojunk@knology.net> - 2017-02-07 10:28 -0600
    Re: USB cabling constraints jrwalliker@gmail.com - 2017-02-07 08:54 -0800
    Re: USB cabling constraints rickman <gnuarm@gmail.com> - 2017-02-07 20:37 -0500
    Re: USB cabling constraints Don Y <blockedofcourse@foo.invalid> - 2017-02-07 20:23 -0700
    Re: USB cabling constraints Robert Baer <robertbaer@localnet.com> - 2017-02-08 21:29 -0800
      Re: USB cabling constraints Kamen Lilov <kamenl@gmail.com> - 2017-02-09 14:01 -0800
  Re: USB cabling constraints Jeff Liebermann <jeffl@cruzio.com> - 2017-02-07 10:39 -0800
  Re: USB cabling constraints "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-02-07 19:06 -0600
    Re: USB cabling constraints Don Y <blockedofcourse@foo.invalid> - 2017-02-07 20:35 -0700
      Re: USB cabling constraints "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-02-08 17:49 -0600
        Re: USB cabling constraints Don Y <blockedofcourse@foo.invalid> - 2017-02-08 20:33 -0700
          Re: USB cabling constraints "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-02-09 16:43 -0600
            Re: USB cabling constraints Don Y <blockedofcourse@foo.invalid> - 2017-02-09 16:18 -0700

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