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Re: ARM/Atmel buses, architecture - Naimi

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On 10/06/16 07:29, Veek. M wrote:
> I don't understand points 2,3,4. In the Harvard Arch, we separate code 
> and data flow. Eg:
> LDI R16, 0F
> 
> 0F is pulled from flash (using the data bus - operand) at the same time 
> as the LDI (via the code bus - opcode). The register R16 is GPR so it's 
> in the CPU.
> 
> What the heck is 2 for:
> 'a set of address buses for accessing the data' ?
> And the others:
> a set of address buses to access the opcodes
> 
> Why do we have:
> In RISC processors, there are four sets of buses
> 
> 
> http://storage8.static.itmages.com/i/16/0610/h_1465535771_9345089_c9fbeb90a9.png
> 
> RISC processors have separate buses for data and code. In all the x86
> processors, like all other CISC computers, there is one set of buses for 
> the address (e.g., A0?A24 in the 80286) and another set of buses for 
> data (e.g., D0?Dl5 in the 80286) carrying opcodes and operands in and 
> out of the CPU. 
> 
> To access any sec-tion of memory, regardless of whether it contains code 
> or data operands, the same address bus and data bus are used. 
> 
> In RISC processors, there are four sets ofbuses:
> (l) a set of data buses for carrying data (operands) in and out of the 
> CPU, (2) a set of address buses for accessing the data, (3) a set of 
> buses to carry the opcodes, and(4) a set of address buses to access the 
> opcodes. The use ofseparate buses for codeand data operands is commonly 
> referred to as Harvard architecture. We examinedthe Harvard architecture 
> of the AVR in the previous section.
> 

The book is explaining things very badly - it is mixing up logical and
physical buses, internal and external buses, and address spaces.  It is
also making terrible generalisations in its distinctions between RISC
and CISC, and appears to have a view of "Harvard vs. von Neumann" from
the 1970's.

It is much more common to talk of a "data bus" as including the address
lines and the data lines needed for reading and writing data, and an
"instruction bus" as including the address lines and data lines needed
for reading instructions and opcodes.  On some systems, such as the AVR,
these are physically separate and access separate memory blocks.  On
most modern cpus, they are physically separate from the cpu core, and
may be connected to independent L0 caches or buffers, but are later
combined in a multiplexer, crosspoint or bus controller, perhaps along
with a unified cache, before connecting to a single memory space.  And
on smaller or older cpus, the pathways may never be independent - there
is just one bus coming out of the core.

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ARM/Atmel buses, architecture - Naimi "Veek. M" <vek.m1234@gmail.com> - 2016-06-10 10:59 +0530
  Re: ARM/Atmel buses, architecture - Naimi rickman <gnuarm@gmail.com> - 2016-06-10 01:44 -0400
  Re: ARM/Atmel buses, architecture - Naimi David Brown <david.brown@hesbynett.no> - 2016-06-10 09:13 +0200
    Re: ARM/Atmel buses, architecture - Naimi Tim Wescott <seemywebsite@myfooter.really> - 2016-06-10 12:22 -0500
      Re: ARM/Atmel buses, architecture - Naimi rickman <gnuarm@gmail.com> - 2016-06-10 14:05 -0400
        Re: ARM/Atmel buses, architecture - Naimi Tim Wescott <seemywebsite@myfooter.really> - 2016-06-10 14:06 -0500
        Re: ARM/Atmel buses, architecture - Naimi David Brown <david.brown@hesbynett.no> - 2016-06-11 02:00 +0200
      Re: ARM/Atmel buses, architecture - Naimi George Neuner <gneuner2@comcast.net> - 2016-06-10 21:07 -0400
        Re: ARM/Atmel buses, architecture - Naimi rickman <gnuarm@gmail.com> - 2016-06-10 22:35 -0400
          Re: ARM/Atmel buses, architecture - Naimi Tim Wescott <tim@seemywebsite.com> - 2016-06-10 22:14 -0500
          Re: ARM/Atmel buses, architecture - Naimi Dimiter_Popoff <dp@tgi-sci.com> - 2016-06-11 14:48 +0300
          Re: ARM/Atmel buses, architecture - Naimi George Neuner <gneuner2@comcast.net> - 2016-06-11 15:51 -0400
            Re: ARM/Atmel buses, architecture - Naimi Dimiter_Popoff <dp@tgi-sci.com> - 2016-06-12 02:13 +0300
              Re: ARM/Atmel buses, architecture - Naimi George Neuner <gneuner2@comcast.net> - 2016-06-11 22:40 -0400
                Re: ARM/Atmel buses, architecture - Naimi Dimiter_Popoff <dp@tgi-sci.com> - 2016-06-12 10:22 +0300
                Re: ARM/Atmel buses, architecture - Naimi George Neuner <gneuner2@comcast.net> - 2016-06-13 10:36 -0400
            Re: ARM/Atmel buses, architecture - Naimi Clifford Heath <no.spam@please.net> - 2016-06-12 11:01 +1000
              Re: ARM/Atmel buses, architecture - Naimi George Neuner <gneuner2@comcast.net> - 2016-06-11 23:50 -0400
              Re: ARM/Atmel buses, architecture - Naimi upsidedown@downunder.com - 2016-06-12 10:13 +0300

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