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Re: What's the maximum RAM size that can be embedded in an ASIC today?

From Don Y <this@isnotme.com>
Newsgroups comp.arch.embedded
Subject Re: What's the maximum RAM size that can be embedded in an ASIC today?
Date 2013-08-28 00:48 -0700
Organization Aioe.org NNTP Server
Message-ID <kvka01$vff$1@speranza.aioe.org> (permalink)
References (2 earlier) <kvg5mk$9ni$1@reader1.panix.com> <a16d2$521bc745$5f6173bc$6888@abuse.newsxs.nl> <521D3B9E.1040704@yahoo.com> <kvjob3$qen$1@speranza.aioe.org> <bp4r191m5941iqi5nii5p1lb8s9v7r1811@4ax.com>

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Hi Robert,

On 8/27/2013 11:07 PM, Robert Wessel wrote:
> On Tue, 27 Aug 2013 19:46:59 -0700, Don Y <this@isnotme.com> wrote:

[attributions elided]

>>>> The post's subject puts a huge constraint on approaches like that:
>>>> It has to happen today.
>>>
>>> Ok then.  I'll change my answer.  It's not possible to fit any amount of
>>> RAM on an ASIC today.  ASIC design cycles take more than one day.
>>
>> Um.... no.  Technically, an FPGA qualifies as an ASIC.  So, you
>> could design and produce a functioning "ASIC" in a single 24 hr
>> period (assuming you had the tools and components in place before
>> you started).
>
> Eh?  By definition, an FPGA is *not* an ASIC.  An FPGA is general
> purpose (FSVO "general purpose") part, and not "Application
> Specific...".

If I gave you a piece of plastic that performed a specific function
when you twiddled certain pins in a certain way would you agree
it was an ASIC?  It's obviously an IC.  It performs a specific
function defined by its intended application.

If you deencapsulated it and found a full custom mask with my
initials in the lower left corner, would you be satisfied?

If, instead, you found a generic SoC with a *masked* ROM would
your opinion change?

What if it was a generic SoC with a FLASH store?  Or, EPROM?

What if it was BBSRAM?

As far as you are concerned, the functionality is rigidly
defined when I put the device into your hands.

What if the SoC was, instead, a sea of gates and the "programming"
was masked?  What about, *electrically* configured?

Ages ago, we used MPU's (not MCU's!) with external *masked* ROM.
Long lead times.  High setup charges.  Big minimum quantities.
Dirt cheap once you got over all that up-front stuff!  But,
*really* hard to change!!  (there were chips produced whose
sole purpose was to "patch ROMs" -- piggy back it onto your circuit
so it would jam *it's* data onto the bus in place of the masked
ROM's... at particular addresses!)

Then, EPROM!  Program it on your premises.  No long lead times.
No minimum quantities.  No setup charges.  Terribly expensive
($25/KB).  Not well suited to large volumes.  But, if you wanted
to change your mind often (e.g., development), perfect choice!

Hmmm... folks really like this convenience!  And, higher volumes,
competition, fab improvements are bringing the cost *way* down!
Unfortunately, the ceramic package is a huge cost penalty.

"Hey, many folks are using these in PRODUCTION, now!  They don't
need to erase/reprogram them.  Why have a window at all?"  Hence
came the OTP parts.  And, if you were really clever, you could
actually *reprogram* these!

[Early in the OTP adoption, we were getting "masked" parts that
were actually OTP's that the manufacturer was programming for
us -- cheaper than running a new batch of a particular mask set]

Repeat with FLASH, etc.

[We used to make *instantly* reprogrammable "ROMs" -- no need to
erase and reprogram as that took a lot of development time -- out
of static RAMs with batteries glued to their backsides along with
some glue logic]

I.e., these are all just cost/manufacturing tradeoffs made by the
customer -- OR BY THE VENDOR.

PLAs have taken the same sort of approach.  Moving from fusible links
(PALs), to EPROM cells, masked metalization layers (sea-of-gates
and STL), etc.  The fixed AND-OR arrays of early devices moving to
more complex macrocells, then generic sea-of-gates and, now, back
towards more "predefined subsystems" interconnected on chip.  (i.e.,
very few designs nowadays are more than SSI+MSI+LSI on the same
die -- but with configurable interconnects)

But, how the interconnects are made is really just a manufacturing
economy. Do you trade off general purpose routing capability for
functional gate real estate, etc.?  Wanna bet the cost point keeps
shifting as geometries shrink and yields improve -- and customers
shift to "OTP-ish" implementations instead of full custom?

Once <whatever> is programmed, it's functionality is defined.
Specific.  If the OP's "RAM requirements" were more modest, he
could give those to someone and receive his ASIC a few hours
later -- guaranteed to perform the application specific functionality
desired AND NOTHING MORE (though the "ASIC" would strongly resemble
an FPGA!  :> )

Do you only consider "full customs" as ASICs?  And, of those, do
designs built from standard cells rate a different/lesser designation?

YMMV, of course.  Until the day you crack open a "full custom"
and find some *programmable* part hiding inside  :>

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Thread

What's the maximum RAM size that can be embedded in an ASIC today? juangui.jg@gmail.com - 2013-08-23 15:44 -0700
  Re: What's the maximum RAM size that can be embedded in an ASIC today? Don Y <this@isnotme.com> - 2013-08-23 16:17 -0700
  Re: What's the maximum RAM size that can be embedded in an ASIC today? rickman <gnuarm@gmail.com> - 2013-08-23 23:18 -0400
  Re: What's the maximum RAM size that can be embedded in an ASIC today? Robert Wessel <robertwessel2@yahoo.com> - 2013-08-23 23:46 -0500
  Re: What's the maximum RAM size that can be embedded in an ASIC today? Paul <paul@pcserviceselectronics.co.uk> - 2013-08-24 09:33 +0100
  Re: What's the maximum RAM size that can be embedded in an ASIC today? upsidedown@downunder.com - 2013-08-24 12:28 +0300
  Re: What's the maximum RAM size that can be embedded in an ASIC today? John Speth <johnspeth@yahoo.com> - 2013-08-26 10:58 -0700
    Re: What's the maximum RAM size that can be embedded in an ASIC today? Grant Edwards <invalid@invalid.invalid> - 2013-08-26 18:10 +0000
      Re: What's the maximum RAM size that can be embedded in an ASIC today? Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> - 2013-08-26 23:23 +0200
        Re: What's the maximum RAM size that can be embedded in an ASIC today? Grant Edwards <invalid@invalid.invalid> - 2013-08-26 21:48 +0000
        Re: What's the maximum RAM size that can be embedded in an ASIC today? John Speth <johnspeth@yahoo.com> - 2013-08-27 16:51 -0700
          Re: What's the maximum RAM size that can be embedded in an ASIC today? Don Y <this@isnotme.com> - 2013-08-27 19:46 -0700
            Re: What's the maximum RAM size that can be embedded in an ASIC today? Robert Wessel <robertwessel2@yahoo.com> - 2013-08-28 01:07 -0500
              Re: What's the maximum RAM size that can be embedded in an ASIC today? Don Y <this@isnotme.com> - 2013-08-28 00:48 -0700
                Re: What's the maximum RAM size that can be embedded in an ASIC today? Robert Wessel <robertwessel2@yahoo.com> - 2013-08-29 16:22 -0500
              Re: What's the maximum RAM size that can be embedded in an ASIC today? Randy Yates <yates@digitalsignallabs.com> - 2013-08-28 08:44 -0400
            Re: What's the maximum RAM size that can be embedded in an ASIC today? Grant Edwards <invalid@invalid.invalid> - 2013-08-28 14:11 +0000
              Re: What's the maximum RAM size that can be embedded in an ASIC today? Paul <paul@pcserviceselectronics.co.uk> - 2013-08-29 09:18 +0100
                Re: What's the maximum RAM size that can be embedded in an ASIC today? Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> - 2013-08-29 10:20 -0400
                Re: What's the maximum RAM size that can be embedded in an ASIC today? Paul <paul@pcserviceselectronics.co.uk> - 2013-08-29 22:40 +0100
                Re: What's the maximum RAM size that can be embedded in an ASIC today? Paul Rubin <no.email@nospam.invalid> - 2013-08-30 01:10 -0700
                Re: What's the maximum RAM size that can be embedded in an ASIC today? Paul <paul@pcserviceselectronics.co.uk> - 2013-08-30 12:40 +0100

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