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Re: Bit Interleaving, Instruction Set Support for

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On 9/9/2011 12:10 PM, Tim McCaffrey wrote:
> In article<7zwrdmaxqg.fsf@ask.diku.dk>, torbenm@diku.dk says...
>>
>> Andrew Reilly<areilly---@bigpond.net.au>  writes:
>>
>>
>>> On recent ARM (perhaps only in the NEON set) there are both "shuffle" and
>>> "deal" instructions: shuffle is your 1:1 interleave and deal is the
>>> reverse (taking an interleaved double-length vector and producing two de-
>>> interleaved results).
>>
>> I think "zip" and "unzip" are better names for these operations.
>>
>> A more general form of zip would be an operation that takes two
>> operands: A bitmask and bit vector.  The bits in the bit vector (from
>> one end) would be positioned at the 1-bits in the bitmask.
>>
>> For example, if the bitmask is 101101 and the bitvector has bits abcdef,
>> then the result would be c0de0f for a right-zip and a0bc0e for a
>> left-zip.
>>
>> Any m:n zip can be made using two of the above and a bitwise or --
>> providing the bit masks are available in registers.
>>
>> The inverse operation would take the bits at the positions indicated by
>> the bitmask and compress them to one end.
>>
>> I'm thinking that both operations could be implemented by a relatively
>> simple modification of a multiplier.
>>
>>         Torben
>
> See http://software.intel.com/file/36945 for the Haswell New Instructions
> (due 2013?) PEXT and PDEP.  They do what you suggest (more or less).
>
> 		- Tim
>



Good point.

This is in part why I am trying to write comp-arch.net: to make some of 
this information easier to find.

E.g. for example I had not realized that Torben's zip and unzip were the 
same as the[[compress bits under mask]] instruction (and accompanying 
[[uncompress bits under mask]], which I had already posted on the wiki 
(http://semipublic.comp-arch.net/wiki/Compress_Bits_Under_Mask)

And [[compress bits under mask]] is in turn the same as the 
[[centrifuge]] instruction that has been done before.  Although IIRC 
Cray's centrifuge was a special unit, not so neatly packaged as an 
instruction.

And these seem to be the same as Intel's [[PEXT]] and [[PDEP]] instructions.

So many different names, for similar concepts.



All of these are [[bit interleave with zero]] instructions.  You can use 
them to do a full bit interleaving by ORing their results.


Or, you can do what Larrabee's vbitinterleave11 and vbitinterleave21 
instructions do - interleave the data directly.



I.e.

    Larrabee bitinterleave 11 and 21:
        * fixed interleaving patterns
        * fewer instructions

    compress/uncompress bits under mask
        * flexible interleaving patterns (also bitfield extraction)
        * but more instructions needed
          to accomplish what Larrabee does in a single instruction

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Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-05 16:23 -0700
  Re: Bit Interleaving, Instruction Set Support for Mark Thorson <nospam@sonic.net> - 2011-09-05 20:07 -0800
    Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-05 21:25 -0700
      Re: Bit Interleaving, Instruction Set Support for Andrew Reilly <areilly---@bigpond.net.au> - 2011-09-06 05:09 +0000
        Re: Bit Interleaving, Instruction Set Support for torbenm@diku.dk (Torben Ægidius Mogensen) - 2011-09-06 10:20 +0200
          Re: Bit Interleaving, Instruction Set Support for Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-09-06 13:28 +0200
            Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-06 11:29 -0700
          Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-06 11:21 -0700
          Re: Bit Interleaving, Instruction Set Support for timcaffrey@aol.com (Tim McCaffrey) - 2011-09-09 19:10 +0000
            Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-10 12:50 -0700
            Re: Bit Interleaving, Instruction Set Support for torbenm@diku.dk (Torben Ægidius Mogensen) - 2011-09-13 10:34 +0200
      Re: Bit Interleaving, Instruction Set Support for Mark Thorson <nospam@sonic.net> - 2011-09-07 12:43 -0800
        Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-10 12:27 -0700
          Re: Bit Interleaving, Instruction Set Support for "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-09-11 21:05 -0700
        Re: Bit Interleaving, Instruction Set Support for EricP <ThatWouldBeTelling@thevillage.com> - 2011-09-10 16:57 -0400
          Re: Bit Interleaving, Instruction Set Support for George Neuner <gneuner2@comcast.net> - 2011-09-10 23:14 -0400
            Re: Bit Interleaving, Instruction Set Support for nmm1@cam.ac.uk - 2011-09-11 10:16 +0100
              Re: Bit Interleaving, Instruction Set Support for EricP <ThatWouldBeTelling@thevillage.com> - 2011-09-11 12:30 -0400
    Re: Bit Interleaving, Instruction Set Support for Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-09-06 13:25 +0200
  Re: Bit Interleaving, Instruction Set Support for Quadibloc <jsavard@ecn.ab.ca> - 2011-09-05 21:02 -0700
  Re: Bit Interleaving, Instruction Set Support for Piotr Wyderski <peter.pan@neverland.mil> - 2011-09-06 14:12 +0200
    Re: Bit Interleaving, Instruction Set Support for Bakul Shah <usenet@bitblocks.com> - 2011-09-06 11:49 -0700
      Re: Bit Interleaving, Instruction Set Support for Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-09-07 11:18 +0200
        Re: Bit Interleaving, Instruction Set Support for Thomas Womack <twomack@chiark.greenend.org.uk> - 2011-09-07 10:54 +0100
          Re: Bit Interleaving, Instruction Set Support for Terje Mathisen <"terje.mathisen at tmsw.no"> - 2011-09-07 20:27 +0200
  Re: Bit Interleaving, Instruction Set Support for MitchAlsup <MitchAlsup@aol.com> - 2011-09-07 12:23 -0700

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