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| Message-ID | <4E15524B.7090509@SPAM.comp-arch.net> (permalink) |
|---|---|
| Date | 2011-07-06 23:29 -0700 |
| From | "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> |
| Organization | comp-arch.net |
| Newsgroups | comp.arch |
| Subject | Re: The Indexed Instruction Problem Solved! |
| References | <b4ebeaa5-411f-4ee8-8a18-71a49e4e0ed3@glegroupsg2000goo.googlegroups.com> |
On 7/6/2011 2:12 PM, MitchAlsup wrote:
> On Tuesday, July 5, 2011 5:58:12 PM UTC-5, Quadibloc wrote:
>> But I'm surprised that the 68020 and the VAX are not included among
>> those that "got it right", because I was pretty sure they did have
>> full base + index + displacement addressing.
>
> In the case of the 68020, while id did have a useful set of addressing modes, their performance was lower than not using the addressing modes. That is microcoded addressing modes were slower than more instructions being used.
This is why I called my undergrad computer project RAMM/RISC/SEISM,
where RAMM stood for "Reduced Addressing Mode Machine".
(I never bought in to the RISC deprecation of divide or FP.)
> PDP-11, VAX, 68K family, National 32K family all got the auto-increment and autodecrement wrong:: in that in many codes there are as many postdecrements as there are predecrements. Favoring one over the others is problematic (even though these directly support stack structures.
Except that pre-increment/decre more general form:
mem_reference[ address_reg := address_reg+scale*index_reg + offset ]
is a form of CSE (Common Subexpression Elimination), saving the result
of the address calculatgion for future use,
whereas post-incrementdecrement is not.
Even if you think of it as
mem_reference[ (old = address_reg,
address_reg = address_reg+scale*index_reg + offset,
old)
]
it still costs more hardware - another bus to carry the address, as well
as the writeback.
>
>> The 360 had a short
>> displacement, and unlike other architectures (including the 68020),
>> there was no option to implicitly shift the index register left to
>> match the data item size.
>
> I basically want all address modes to take the same amount of time in the address generation pipeline.
>
> The 360 is only burdened with 12-bit positive only offsets, and we saw a significant benefit to 16-bit +/- offsets in the RISC days; and it was not until the x86-64 days that I became fully aware of how powerful the x86 instruction set was when powered by multiple full width instruction decoders (that give the property of the previous paragraph).
>
> In a RICS-like instruction set one must fundamentally choose the width of the offset field (typically 16 but occasionally something strange like 13). Not so with a x86-like instruction set and offsets (n.e. displacements) can be 8, 16, 32 bits wide dynamically selected by modes and prefix codes. But they all retain the "take the same time" property in the address generation stage.
>
> I suspect that a modern VAX-like instruction set with a tripple ported data cache could be facillitated to have the necessary property that all address generations take the same amount of time (by dropping the indirect modes, and leaving out the COBOL support instructions.) VAX was HEAVILY burdened<to its demise> with the high overhead CALL/RET instructions.
>
> Mitch
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Re: The Indexed Instruction Problem Solved! MitchAlsup <MitchAlsup@aol.com> - 2011-07-06 14:12 -0700
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-06 15:48 -0700
Re: The Indexed Instruction Problem Solved! EricP <ThatWouldBeTelling@thevillage.com> - 2011-07-06 20:36 -0400
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-06 23:29 -0700
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-06 23:31 -0700
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-06 23:38 -0700
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-06 23:39 -0700
Re: The Indexed Instruction Problem Solved! timcaffrey@aol.com (Tim McCaffrey) - 2011-07-14 01:36 +0000
Re: The Indexed Instruction Problem Solved! Stephen Fuld <SFuld@alumni.cmu.edu.invalid> - 2011-07-07 08:12 -0700
Re: The Indexed Instruction Problem Solved! EricP <ThatWouldBeTelling@thevillage.com> - 2011-07-07 12:24 -0400
Re: The Indexed Instruction Problem Solved! John Levine <johnl@iecc.com> - 2011-07-08 01:29 +0000
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-07 18:53 -0700
Re: The Indexed Instruction Problem Solved! John Levine <johnl@iecc.com> - 2011-07-08 02:17 +0000
Re: The Indexed Instruction Problem Solved! EricP <ThatWouldBeTelling@thevillage.com> - 2011-07-09 13:15 -0400
Re: The Indexed Instruction Problem Solved! John Levine <johnl@iecc.com> - 2011-07-09 18:37 +0000
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-09 11:53 -0700
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-09 11:55 -0700
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-09 11:49 -0700
Re: The Indexed Instruction Problem Solved! Chris Jones <clj@panix.com> - 2011-07-09 16:21 -0400
Re: The Indexed Instruction Problem Solved! Joe Chisolm <jchisolm6@earthlink.net> - 2011-07-07 13:19 -0500
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-07 12:11 -0700
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-07 12:13 -0700
Re: The Indexed Instruction Problem Solved! jsavard@excxn.aNOSPAMb.cdn.invalid (John Savard) - 2011-07-07 19:32 +0000
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-07 04:09 -0700
Re: The Indexed Instruction Problem Solved! Brett Davis <ggtgp@yahoo.com> - 2011-07-12 18:31 -0500
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-13 22:31 -0700
Re: The Indexed Instruction Problem Solved! mac <acolvin@efunct.com> - 2011-07-17 15:31 +0000
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-17 09:50 -0700
Re: The Indexed Instruction Problem Solved! Andrew Reilly <areilly---@bigpond.net.au> - 2011-07-17 23:26 +0000
Re: The Indexed Instruction Problem Solved! Brett Davis <ggtgp@yahoo.com> - 2011-07-17 19:52 -0500
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-17 18:22 -0700
Re: The Indexed Instruction Problem Solved! "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-07-17 21:33 -0700
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-18 06:34 -0700
Re: The Indexed Instruction Problem Solved! Stephen Fuld <SFuld@alumni.cmu.edu.invalid> - 2011-07-18 09:22 -0700
Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-18 14:13 +0100
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-18 07:27 -0700
Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-18 16:22 +0100
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-18 09:56 -0700
Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-18 17:43 +0100
Re: The Indexed Instruction Problem Solved! Quadibloc <jsavard@ecn.ab.ca> - 2011-07-18 14:58 -0700
Re: The Indexed Instruction Problem Solved! nmm1@cam.ac.uk - 2011-07-19 07:22 +0100
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