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[ecsi-2] Program available > ESLsyn Conference > June 2-3, San Francisco, Co-located with DAC

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[http://www.ecsi.org/sites/default/files/images/ESLsyn-small.jpg]<http://www
.ecsi.org/eslsyn>
Electronic System Level Synthesis Conference
Early registration deadline: May 7!
Program now available on the ECSI website
June 2-3, 2012
San Francisco, California, USA
General Co-Chairs:
Sandeep K. Shukla, Virginia Tech, US & Philippe Coussy, Lab-STICC, FR
Program Co-Chairs:
Jens Brandt, TU Kaiserslautern, DE & Achim Rettberg, U. of Oldenburg, DE
Organization Chair: Adam Morawiec, ECSI, FR

www.ecsi.org/eslsyn

ESLsyn is organized with the technical co-sponsorship
of IEEE & IEEE Council on Electronic Design Automation (CEDA)
[http://www.ecsi.org/sites/default/files/images/IEEE.gif]
[http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg]


Preliminary Program

SATURDAY, JUNE 2

09:00  Keynote 1: Satnam Singh, Google

10:00  Industrial Talk: Michael McNamara, Cadence

11:00  Session 1: High-Level Synthesis

Trimmed VLIW: Moving Application Specific Processors Towards High Level
Synthesis
Janarbek Matai, Jason Oberg, Ali Irturk, Ryan Kastner (University of
California, San Diego), and Taemin Kim (Intel)

A Model-Based Inter-Process Resource Sharing Approach for High-Level
Synthesis of Dataflow Graphs
Christian Zebelein and Christian Haubelt (University of Rostock), Joachim
Falk and Christian Haubelt (University of Erlangen-Nuremberg)

13:00  Keynote 2: (TBC)

14:00  Session 2: Modelling

Synthesizing Embedded Software with Safety Wrappers through Polyhedral
Analysis in a Polychronous Framework
Mahesh Nanjundappa, Matthew Kracht, Julien Ouy and Sandeep Shukla (Virginia
Tech)

Automatic Generation of Observers from MARTE/CCSL
Frédéric Mallet (Université Nice-Sophia Antipolis)

15:15  Invited Talk: Arkadeb Ghosal, National Instruments

16:15  Demo Session

SUNDAY, JUNE 3

09:00  Keynote 3: Stephen Edwards, Columbia University

10:00  Invited Talk: (TBC)

11:00  Special Session
Achim Rettberg, University of Oldenburg
William Fornaciari, PoliMi
Franco Fummi, University of Verona

13:00  Keynote 4: John Sanguinetti, Forte DS

14:00  Session 3: High-Level Synthesis

High-level Synthesis with Multi-Cycles Chaining and Behavior-level Timing
Extraction
Hongbin Zheng, Qingrui Liu, Junqi Deng, Junyi Li, Tao Su, Dihu Chen and
Zixin Wang (Sun Yat-sen University)

Transaction-Accurate Interface Scheduling in High-Level Synthesis
John Sanguinetti, Michael Meredith and Sean Dart (Forte DS)

15:15  Session 4: MPSoCs

Multi-layer Configuration Exploration of MPSoCs for Streaming Applications
Deepak Mishrad, Rainer Doemer, Elaheh Bozorgzadeh, Yasaman Samei and Nga
Dang (University of California, Irvine)

Process Variation-aware Task Replication for Throughput Optimization in
Configurable MPSoCs
Love Singhal (Synopsys), Hessam Kooti and Eli Bozorgzadeh (University of
California, Irvine)

16:15  Demo Session


Demonstration Opportunities

ECSI Member Opportunities
Opportunities for ECSI members include:

·         Free of charge demonstration booths!

·         Free publicity of your organization!

·         Reduced registration rates!
Contact us now to benefit from these opportunities or to find out more
about becoming an ECSI Member!
Sponsorship Opportunities
We would also like to extend an invitation to industrial companies and
university organizations alike to sponsor the 2012 ESLsyn Conference to gain
the same benefits as ECSI Members.
Demonstrators Include
National Instruments Lab at Berkeley
Cadence
Forte DS
COMPLEX Project
Calypto (TBC)


Description

The ever-increasing need for enhanced productivity in designing highly
complex electronic systems drives the evolution of design methods beyond the
traditional approaches. Virtual prototyping, design space exploration and
system synthesis with the goal of optimized and functionally correct product
implementations are needed for designing both HW and SW parts. ESL design
does not only provide system architects with the right tools to make the
right decisions about the system architecture, it includes the methodologies
and techniques that correlate the ESL model. A well-connected
ESL-to-implementation design flow is needed.

The system design teams expect newer and more efficient methods and tools
supporting better management of the design complexity and reduction of the
design cycle time all together, breaking the trend to compromise on the
evaluation of various design implementation options. Designing at higher
levels of abstraction is a viable way to better cope with the system design
complexity, to verify earlier in the design process and to increase code
reuse.

The Electronic System Level Synthesis Conference ESLsyn focuses on automated
system design methods that enable efficient modelling of systems to provide
the capability to synthesize HW platforms and embedded software with
particular aspects related to synthesis.

Co-located with DAC
The Design Automation Conference (DAC) is the premier event for the design
of electronic circuits and systems, and for EDA and silicon solutions. Now
in its 49th year, DAC features a wide array of technical presentations, as
well as more than 200 of the leading electronics design suppliers in a
colorful, well-attended trade show that, literally, attracts stakeholders
from around the world.
DAC is where the IC Design and EDA ecosystem learns, networks, and does
business. DAC is also where the latest technical research is presented. DAC
covers all topics related to the design complex systems on chip: Embedded
System design and verification down to physical layout verification & test.


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[ecsi-2] Program available > ESLsyn Conference > June 2-3, San Francisco, Co-located with DAC "info@ecsi.org" <info@ecsi.org> - 2012-05-10 15:09 +0000

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