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Re: Operating System Design

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Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:

> ruben safir <ruben@mrbrklyn.com> writes:
>
>> I'm wondering if anyone has a background in operating system design.
>> I'm taking a class is OS's and the text is
>>
>> OPERATING
>> SYSTEM
>> CONCEPTS
>> ABRAHAM SILBERSCHATZ
>> 9th edition, and it says something that is puzzling me
>>
>>
>>
>> "Interrupts are an important part of a computer architecture. Each
>> computer design has its own interrupt mechanism, but several functions
>> are common. The interrupt must transfer control to the appropriate
>> interrupt service routine. The straightforward method for handling this
>> transfer would be to invoke a generic routine to examine the interrupt
>> information. The routine, in turn, would call the interrupt-specific
>> handler. However, interrupts must be handled quickly"
>>
>> " Since only a predefined number of interrupts is possible, a table of
>> pointers to interrupt routines can be used instead*** to provide the
>> necessary speed. The interrupt routine is called indirectly through the
>> table, with no intermediate routine needed. Generally, the table of
>> pointers is stored in low memory (the first hundred or so locations).
>> These locations hold the addresses of the interrupt service routines for
>> the various devices. This array, or interrupt vector, of addresses is
>> then indexed by a unique device number, given with the interrupt
>> request, to provide the address of the interrupt service routine for
>> the interrupting device. Operating systems as different as Windows and
>> UNIX dispatch interrupts in this manner."
>>
>>
>> ***  Instead of what?  Just because you have a table of pointers to
>> routines doesn't change the need for a routine, a generic routine
>> perhaps, from accessing that table.
>
> In an interrupt vector table like he's describing, the hardware indexes
> the table directly and jumps straight to the ISR without any software
> intervention before it gets there.

After reading some of the other responses, I'll give a concrete example
(which sounds like the machine he has in mind):  the interrupt mechanism
on the old DEC PDP-11.

On the PDP-11, a device requested an interrupt by asserting a bus
request line.  The CPU would respond by asserting a corresponding bus
grant line (there was a mechanism for resolving multiple simultaneous
interrupt requests, which is not relevant here).

After receiving the bus grant, the device would place a memory address
on the bus address lines.  This was the address of the device's
"interrupt vector".

The CPU would retrieve a new program counter (PC) and processor status
word (PSW) from the four bytes at this address, push the old PC and PSW
on the stack, and begin execution at the new PC.

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Operating System Design ruben safir <ruben@mrbrklyn.com> - 2015-01-29 17:11 -0500
  Re: Operating System Design "Vince Coen" <VBCoen@gmail.com> - 2015-01-29 22:29 +0000
  Re: Operating System Design Lew Pitcher <lew.pitcher@digitalfreehold.ca> - 2015-01-29 17:38 -0500
  Re: Operating System Design Joe Pfeiffer <pfeiffer@cs.nmsu.edu> - 2015-01-29 16:07 -0700
    Re: Operating System Design Joe Pfeiffer <pfeiffer@cs.nmsu.edu> - 2015-01-29 16:16 -0700
  Re: Operating System Design David Brown <david.brown@hesbynett.no> - 2015-01-30 09:00 +0100
    Re: Operating System Design ruben safir <ruben@mrbrklyn.com> - 2015-02-01 19:34 -0500

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