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Re: Interrupts in OoO

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EricP <ThatWouldBeTelling@thevillage.com> posted:

> On 2026-Oct-26 13:17, Robert Finch wrote:
> > On 2026-10-26 11:06 a.m., EricP wrote:
> >> On 2026-Oct-25 11:53, Scott Lurndal wrote:
> >>> MitchAlsup <user5857@newsgrouper.org.invalid> writes:
----------snip-----------

> Precise means the processor state corresponds with a sequential model
> of program execution where one instruction completes before the next begin.
> 
> Synchronous means that the saved state corresponds with the particular
> instruction that triggered the state or the instruction after it.
> For a Fault the state correspond to the triggering instruction.
> For a Trap the state corresponds to the instruction after the
> triggering instruction.
> All exceptions, whether faults or traps, are synchronous.
> 
> Asynchronous means that the state does not correspond with any
> particular instruction. All Interrupts are asynchronous.
> 
> For an asynchronous Interrupt or synchronous Exception to be
> restartable it must be precise.

Some architectures defined "continue" model of returning from exceptions
{68000} where enough state was saved so the ESR could finish the failed
instruction and then continue onward with the next instruction.

Both seem "workable" while precise has won overall.
 
> Each of Exceptions and Interrupts have well defined behaviour.
> Exceptions only have one delivery mechanism whereas Interrupts might
> have a variety of Interrupt controllers each with its own behavior.
> 
> They can also be quite frequent and I didn't want to burden their
> dispatching mechanisms with the extra overhead of also dealing with
> potential errors that might infrequently occur.
> In both cases I would use a variation on branch-and-link to a hardware
> state save and generated RIP address so there are no memory references
> during the internal state change. This means no double- or triple-faults
> and potentially a 1 clock state change.
> 
> The problem with errors is that their behaviour is all over the place.
> A store operation to memory or device marked as write-through would be
> synchronous with the ST instruction and any errors detected could be
> associated back to the ST instruction.
> A store operation to memory marked as write-back is asynchronous and
> can be performed long after the ST instruction has retired and
> been removed from the core.
> 
> An ECC memory error can be detected and maybe corrected by the
> error scavenger sweep and not associated with any instruction at all.
> 
> Some devices change state when read. For example a UART receive
> buffer can be FIFO queue and reading it consumes the first entry.
> If there was a bus parity error after a successful read of the
> FIFO then one may or may not want to retry the operation.
> 
> By putting infrequent Errors off in their own bucket they can be
> dealt with on a case by case basis without burdening the frequent
> occurance delivery mechanisms for Exceptions and Interrupts.
> 

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Re: Interrupts in OoO (was: Microarchitectural support for counting) quadibloc@invalid.com (John Savard) - 2026-10-23 23:57 +0000
  Re: Interrupts in OoO Robert Finch <robfi680@gmail.com> - 2026-10-23 21:12 -0400
  Re: Interrupts in OoO (was: Microarchitectural support for counting) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-24 19:20 +0000
    Re: Interrupts in OoO (was: Microarchitectural support for counting) scott@slp53.sl.home (Scott Lurndal) - 2026-10-25 15:53 +0000
      Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-26 11:06 -0400
        Re: Interrupts in OoO Robert Finch <robfi680@gmail.com> - 2026-10-26 13:17 -0400
          Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-26 17:03 -0400
            Re: Interrupts in OoO "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-26 14:14 -0700
              Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-28 14:39 -0400
                Re: Interrupts in OoO "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-28 15:10 -0700
                Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-29 14:50 -0400
            Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 16:48 +0000
        Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 16:35 +0000
          Re: Interrupts in OoO scott@slp53.sl.home (Scott Lurndal) - 2026-10-27 18:33 +0000
            Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 21:07 +0000
              Re: Interrupts in OoO scott@slp53.sl.home (Scott Lurndal) - 2026-10-27 21:17 +0000
                Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-28 15:35 +0000
                Re: Interrupts in OoO George Neuner <gneuner2@comcast.net> - 2026-10-28 14:34 -0400
                Re: Interrupts in OoO scott@slp53.sl.home (Scott Lurndal) - 2026-10-28 20:16 +0000
                Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-29 02:17 +0000
                Re: Interrupts in OoO "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2026-10-28 21:21 -0700
                Re: Interrupts in OoO George Neuner <gneuner2@comcast.net> - 2026-10-29 21:49 -0400
              Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-28 14:57 -0400
                Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-29 02:27 +0000
          Re: Interrupts in OoO EricP <ThatWouldBeTelling@thevillage.com> - 2026-10-28 14:19 -0400
            Re: Interrupts in OoO MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-28 19:02 +0000
  Re: Interrupts in OoO (was: Microarchitectural support for counting) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-10-26 17:45 +0000
    Re: Interrupts in OoO (was: Microarchitectural support for counting) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-10-27 16:39 +0000

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