Maybe they should have named it NVIDIA Einstein [Rossy Boy Toe Sucking] (Was: The invention of vector and matrix registers [NVIDIA Volta])

From	Mild Shock <janburse@fastmail.fm>
Newsgroups	sci.logic, comp.lang.prolog, sci.physics
Subject	Maybe they should have named it NVIDIA Einstein [Rossy Boy Toe Sucking] (Was: The invention of vector and matrix registers [NVIDIA Volta])
Date	2026-07-27 17:12 +0200
Message-ID	<1147sgk$geia$1@solani.org> (permalink)
References	(5 earlier) <11476i7$ftjl$2@solani.org> <11477a4$fu5f$2@solani.org> <1147evl$glbs$2@solani.org> <1147f1f$glbs$3@solani.org> <M-KdneYpK_8w8fr3nZ2dnZfqnPSdnZ2d@giganews.com>

Cross-posted to 3 groups.

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Hi,

I guess Rossy Boys mother was so disappointed
in the 50's that is son didn't become the
next Einstain, physics was the ultinate idol,

so that Rossy Boy was left rotting in the
basement. But Rossy Boys indoctrination was
not spurious, he now is conditioned on

Einstein. Maybe NVIDIA should have named
its Tesla V100 card NVIDIA Einstein. You would
then see Rossy Boy toe sucking the graphic

card, in his pyjamas in the basement.

Bye

Ross Finlayson schrieb:
> On 07/27/2026 04:22 AM, Mild Shock wrote:
>> Hi,
>>
>> But the example gives also way to vector
>> and matrix registers. The int[] X and
>> int[] Y could be also held in vector
>>
>> registers. Compilers can also optimize
>> away int[] Y, and use a inline modification,
>> in case X isn't used later, then playing
>>
>> the role of Y:
>>
>> vec_mul_add(X, 2, 3, X)
>>
>> Vector and matrix registers in modern GPUs
>> emerged from distinct architectural milestones:
>> vector-like register files developed with
>> early programmable 3D vertex/pixel pipelines
>>
>> in the late 1990s to early 2000s. While
>> dedicated multi-dimensional matrix registers
>> (Tensor Cores/Matrix Cores) were invented by
>> NVIDIA in 2017, starting with the Tesla
>>
>> V100 (Volta microarchitecture):
>>
>>  From Volta To Blackwell
>> https://newsletter.semianalysis.com/p/nvidia-tensor-core-evolution-from-volta-to-blackwell 
>>
>>
>>
>> You see the scheduling of tensure core occupation
>> scheduling in the above article, including memory
>> and register flow, following the section:
>>
>> MMA Instruction Overview
>>
>> It went through a couple of generations, leading
>> to Tensor Memory (TMEM) and collective operations,
>> basically realizing the PIM idea:
>>
>> Processing-in-Memory Tutorials
>> https://www.sigarch.org/processing-in-memory-tutorials-experiences-from-past-two-years-and-thoughts-looking-forward/ 
>>
>>
>>
>> Have Fun!
>>
>> Bye
> That's bullshit, and alike those talking heads that
> sniff their way into talking about many-core jumbo-trons,
> the super-scalar is as old as the scalar and Cray and examples alike
> the Connection Machine what made all the craze of neural nets
> is old-wrapped-as-new.
> 
> Fabless chips did it already.
> 
> 
> Data centers should pay a 10000% excise on electricity,
> wherever it comes from, a natural regulator of inverted economies.
> 
> And by ten thousand percent I really mean a ten thousand percent.
> 
>

Thread

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      The Koan of pi-WAM queues [FORTRAN-S] (Re: Not SIMD, a MIMD design for NVIDIA Volta) Mild Shock <janburse@fastmail.fm> - 2026-07-26 19:54 +0200
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        Re: The Koan of pi-WAM queues [FORTRAN-S] (Re: Not SIMD, a MIMD design for NVIDIA Volta) Mild Shock <janburse@fastmail.fm> - 2026-07-27 09:16 +0200
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                The invention of vector and matrix registers [NVIDIA Volta] (Re: AI accelerator extend from GPU to CPU [Zero Copying]) Mild Shock <janburse@fastmail.fm> - 2026-07-27 13:22 +0200
                Re: The invention of vector and matrix registers [NVIDIA Volta] (Re: AI accelerator extend from GPU to CPU [Zero Copying]) Ross Finlayson <ross.a.finlayson@gmail.com> - 2026-07-27 07:34 -0700
                Maybe they should have named it NVIDIA Einstein [Rossy Boy Toe Sucking] (Was: The invention of vector and matrix registers [NVIDIA Volta]) Mild Shock <janburse@fastmail.fm> - 2026-07-27 17:12 +0200
                Re: The invention of vector and matrix registers [NVIDIA Volta] (Re: AI accelerator extend from GPU to CPU [Zero Copying]) R Kym Horsell <kym@sdf.com> - 2026-07-27 15:43 +0000
                Re: The invention of vector and matrix registers [NVIDIA Volta] (Re: AI accelerator extend from GPU to CPU [Zero Copying]) R Kym Horsell <kymhorsell@gmail.com> - 2026-07-27 15:46 +0000
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