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Re: Achieving 98% efficiency in a boost converter, RIS-767, errata

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  Re: Achieving 98% efficiency in a boost converter, RIS-767, errata Winfield Hill <hill@rowland.harvard.edu> - 2017-05-27 10:21 -0700
    Re: Achieving 98% efficiency in a boost converter, RIS-767, errata legg <legg@nospam.magma.ca> - 2017-06-17 15:46 -0400
      Re: Achieving 98% efficiency in a boost converter, RIS-767, errata Winfield Hill <hill@rowland.harvard.edu> - 2017-06-17 16:20 -0700
        Re: Achieving 98% efficiency in a boost converter, RIS-767, errata legg <legg@nospam.magma.ca> - 2017-06-19 11:50 -0400
        Re: Achieving 98% efficiency in a boost converter, RIS-767, errata legg <legg@nospam.magma.ca> - 2017-06-19 11:57 -0400
          Re: Achieving 98% efficiency in a boost converter, RIS-767, errata Winfield Hill <hill@rowland.harvard.edu> - 2017-06-20 12:28 -0700

#462003 — Re: Achieving 98% efficiency in a boost converter, RIS-767, errata

Winfield Hill wrote...
>
> ... RIS-767 with 20 chopped-up flip-chip
> daughterboards is on its way.

 Have found two errors on the RIS-767 so far (27May):

 1)  U2, an important switch choice, is fine with
 TI's ts3a24159dg dual 3.3-volt 0.2-ohm spdt.  But
 the ts5a22362dg dual 5-volt 0.5-ohm spdt is no-go.
 Awwk, TI swapped the control and NC pins!   This
 also applies to U27 on flip-chip G: ignore the
 TS5A22362 silk-screen label and use TS3A24159DG.

 Haha, ts3a will likely out-perform the ts5a anyway.
 We may find out, Rob Legg has made cut-jump fixes.

 2)  U19, the cute 0.5A MAX17222ELT boost-converter,
 oops, totally wrong pinout, my fault, no excuse.

 All the other IC footprint pinouts have passed a
 double check.   My apologies for the errors.

 3)  Not an error exactly, more a typo, but the node
 marked PWM on the schematic, which travels all over
 the place, is actually an inverted logic signal,
 *PWM.   Or fPWM, /PWM, PWM', !PWM, or your choice.
 (note: R1 and R2 program U1 for inverted-out mode.)

 4) My convention, showing switches in their logic-HI
 position, can be confusing, logic-LO is more common.

 Updated schematic (with lots of added annotation),
 plus an errata page will be posted to dropbox.
 Labels and U19 will be fixed in the next PCB pass.
 U27 on flip-chip G2 will be rewired for TS5A22362.
    


-- 
 Thanks,
    - Win

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#464865

On 27 May 2017 10:21:18 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>Winfield Hill wrote...
>>
>> ... RIS-767 with 20 chopped-up flip-chip
>> daughterboards is on its way.
>
> Have found two errors on the RIS-767 so far (27May):
>
> 1)  U2, an important switch choice, is fine with
> TI's ts3a24159dg dual 3.3-volt 0.2-ohm spdt.  But
> the ts5a22362dg dual 5-volt 0.5-ohm spdt is no-go.
> Awwk, TI swapped the control and NC pins!   This
> also applies to U27 on flip-chip G: ignore the
> TS5A22362 silk-screen label and use TS3A24159DG.
>
> Haha, ts3a will likely out-perform the ts5a anyway.
> We may find out, Rob Legg has made cut-jump fixes.
>
> 2)  U19, the cute 0.5A MAX17222ELT boost-converter,
> oops, totally wrong pinout, my fault, no excuse.
>
> All the other IC footprint pinouts have passed a
> double check.   My apologies for the errors.
>
> 3)  Not an error exactly, more a typo, but the node
> marked PWM on the schematic, which travels all over
> the place, is actually an inverted logic signal,
> *PWM.   Or fPWM, /PWM, PWM', !PWM, or your choice.
> (note: R1 and R2 program U1 for inverted-out mode.)
>
> 4) My convention, showing switches in their logic-HI
> position, can be confusing, logic-LO is more common.
>
> Updated schematic (with lots of added annotation),
> plus an errata page will be posted to dropbox.
> Labels and U19 will be fixed in the next PCB pass.
> U27 on flip-chip G2 will be rewired for TS5A22362.
>   
Win,

Given the recent results for TS5A22362 and ungapped EP13 choke, might
it not be a good idea to generate some kind of formatted standard test
report for the RIS767?

This could guide measurement collection procedures/targets, assist in
the immediate digestion of collected data and be a step in
coordination of results at a later date.

It would have to be pretty extensive, even perhaps  going as far as to
include standard equipment lists (serial# ? cal date ?) I'm not
suggesting a form for recording raw data - that would just be torture.

Sometimes more (iterations) is actually less. You might have to
request specific trials.......to either avoid duplication or to
attempt it.

It'd also maybe cut down on explanations/justifications required in
distribution of 'standard reports' between participants.

Rob Legg

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#464885

legg wrote...
>
>On 27 May 2017 10:21:18 -0700, Winfield Hill
><hill@rowland.harvard.edu> wrote:
>
>>Winfield Hill wrote...
>>>
>>> ... RIS-767 with 20 chopped-up flip-chip
>>> daughterboards is on its way.
>>
>> Have found two errors on the RIS-767 so far (27May):
>>
>> 1)  U2, an important switch choice, is fine with
>> TI's ts3a24159dg dual 3.3-volt 0.2-ohm spdt.  But
>> the ts5a22362dg dual 5-volt 0.5-ohm spdt is no-go.
>> Awwk, TI swapped the control and NC pins!   This
>> also applies to U27 on flip-chip G: ignore the
>> TS5A22362 silk-screen label and use TS3A24159DG.
>>
>> Haha, ts3a will likely out-perform the ts5a anyway.
>> We may find out, Rob Legg has made cut-jump fixes.
>>
>> 2)  U19, the cute 0.5A MAX17222ELT boost-converter,
>> oops, totally wrong pinout, my fault, no excuse.
>>
>> All the other IC footprint pinouts have passed a
>> double check.   My apologies for the errors.
>>
>> 3)  Not an error exactly, more a typo, but the node
>> marked PWM on the schematic, which travels all over
>> the place, is actually an inverted logic signal,
>> *PWM.   Or fPWM, /PWM, PWM', !PWM, or your choice.
>> (note: R1 and R2 program U1 for inverted-out mode.)
>>
>> 4) My convention, showing switches in their logic-HI
>> position, can be confusing, logic-LO is more common.
>>
>> Updated schematic (with lots of added annotation),
>> plus an errata page will be posted to dropbox.
>> Labels and U19 will be fixed in the next PCB pass.
>> U27 on flip-chip G2 will be rewired for TS5A22362.
>>   
>Win,
>
>Given the recent results for TS5A22362 and ungapped EP13 choke, might
>it not be a good idea to generate some kind of formatted standard test
>report for the RIS767?
>
>This could guide measurement collection procedures/targets, assist in
>the immediate digestion of collected data and be a step in
>coordination of results at a later date.
>
>It would have to be pretty extensive, even perhaps  going as far as to
>include standard equipment lists (serial# ? cal date ?) I'm not
>suggesting a form for recording raw data - that would just be torture.
>
>Sometimes more (iterations) is actually less. You might have to
>request specific trials.......to either avoid duplication or to
>attempt it.
>
>It'd also maybe cut down on explanations/justifications required in
>distribution of 'standard reports' between participants.
>
>Rob Legg

 I think that's a great idea!  Why don't you make one!
 You can populate it with your own data as a test case.


-- 
 Thanks,
    - Win

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#465016

On 17 Jun 2017 16:20:50 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>legg wrote...
<snip>

>>>
>>> Updated schematic (with lots of added annotation),
>>> plus an errata page will be posted to dropbox.
>>> Labels and U19 will be fixed in the next PCB pass.
>>> U27 on flip-chip G2 will be rewired for TS5A22362.
>>>   
>>Win,
>>
>>Given the recent results for TS5A22362 and ungapped EP13 choke, might
>>it not be a good idea to generate some kind of formatted standard test
>>report for the RIS767?
>>
>>This could guide measurement collection procedures/targets, assist in
>>the immediate digestion of collected data and be a step in
>>coordination of results at a later date.
>>
>>It would have to be pretty extensive, even perhaps  going as far as to
>>include standard equipment lists (serial# ? cal date ?) I'm not
>>suggesting a form for recording raw data - that would just be torture.
>>
>>Sometimes more (iterations) is actually less. You might have to
>>request specific trials.......to either avoid duplication or to
>>attempt it.
>>
>>It'd also maybe cut down on explanations/justifications required in
>>distribution of 'standard reports' between participants.
>>
>>Rob Legg
>
> I think that's a great idea!  Why don't you make one!
> You can populate it with your own data as a test case.

Without some kind of feedback on where the presented data range 
and report either succeed or fail, I'd be groping at straws. 

More than 75% of my time, so far, has just gone into correlation 
of shunt and meter readings, permanently-attached instrumentation side
effects and control current/board routing influences - and I still
couldn't get much output that made sense below 10mA.

I'd hate to have to orchestrate such an ineffective procedure, before
the first active measurement trial could start, or account for
variations which might arise as more locations were populated, or the
board was spun. Hopefully, the board spin can cut down on that
nonsense.

The report form needs to be directed towards goals, while providing
sufficient trend visualization to allow analysis within and between
series of trials. The single source and load condition doesn't even
reflect the initial real-world field problem - so aiming at the first
without examining conditions that span the two seems a little short
sighted. Without an accurate aim ( ie - not a single load condition)
you run the risk of having to repeat work for that reason alone.

Output format is heavily influenced by those parameters that can be
controlled over the series of measurements. Open loop frequency and 
duty cycle are provided, though this has to be manually set by
eyeballing a scope or trusting another measurement instrument.

It was a real bug-bear providing anything like a constant voltage
source. The employment of remote sensing (and multi-turn manual
adjustment for manually adjusted hardware) is probably going to be
unavoidable.

Setting the output voltage through an internal regulation loop might 
be useful in a commercial trial, but would be blind to point-of-load
conditions that a PV power source rightly expects. An external
constant voltage shunt regulator might make more sense, if the remote
sensing issues for such a means of regulation can be addressed 

I found a constant current load to be invaluable in data
cross-referencing, however this suffered from all the usual issues of
low voltage operation and control current infection. It is a
relatively simple matter converting this to shunt voltage regulation,
albeit with the same issues.

In any event, your feedback from any attempt to apply currently
collected data to the application issue is essential to reducing waste
in subsequent trials. Also, the issue of a board spin is not a small
one. The rerouting of power and control ground traces; the
reassessment of test measurement point will influence As populating
the test bed location and connectorization; the practical tolerances
of built-in instrumentation or Arduino capability will all affect the
test procedures required to fulfill the purpose of a standard test
report. 

With single board BOM components running at $70 a pop, the choice to
populate a second board or to wait for a respin, will also need your
feedback.

RL
   

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#465017

On 17 Jun 2017 16:20:50 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>legg wrote...

The second to last para should read:

In any event, your feedback from any attempt to apply currently
collected data to the application issue is essential to reducing waste
in subsequent trials. Also, the issue of a board spin is not a small
one. The rerouting of power and control ground traces; the
reassessment of test measurement point location and connectorization;
the practical tolerances of built-in instrumentation or Arduino
capability will all affect the test procedures required to fulfill the
purpose of a standard test report.

*ing portable PC touchpads....grumble grumble

RL

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#465078

legg wrote...
>
>On 17 Jun 2017 16:20:50 -0700, Winfield Hill
><hill@rowland.harvard.edu> wrote:
>
>>legg wrote...
>
>The second to last para should read:
>
>In any event, your feedback from any attempt to apply currently
>collected data to the application issue is essential to reducing waste
>in subsequent trials. Also, the issue of a board spin is not a small
>one. The rerouting of power and control ground traces; the
>reassessment of test measurement point location and connectorization;
>the practical tolerances of built-in instrumentation or Arduino
>capability will all affect the test procedures required to fulfill the
>purpose of a standard test report.
>
>*ing portable PC touchpads....grumble grumble
>
>RL

 My idea is restrict my measurements to an appropriate
 measuring region, not necessarily fully determined by
 an external goal, but more by the parts at hand.  For
 example if you get best results (hopefully near 98%)
 with a 50mA load, rather than 10mA, fine!   Trying
 various inductors, different MOSFETs, different
 frequencies, voltages and currents, etc., is the
 whole idea of an adjustable "test bed".

 The RIS-767 is for low-voltage testing.  It's limited
 to a range of 0.3 to 4V input and up to 5V max output,
 except for up to 15V out, with certain restrictions.
 


-- 
 Thanks,
    - Win

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