Groups > sci.electronics.design > #430957 > unrolled thread

LDO

Started by	John Larkin <jjlarkin@highlandtechnology.com>
First post	2016-10-11 22:09 -0700
Last post	2016-10-13 18:24 -0500
Articles	20 on this page of 43 — 14 participants

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  LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-11 22:09 -0700
    Re: LDO Robert Loos <1209@baer-gmbh.com> - 2016-10-12 09:49 +0200
      Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 08:31 -0700
        Re: LDO bitrex <bitrex@de.lete.earthlink.net> - 2016-10-12 22:47 -0400
        Re: LDO John S <Sophi.2@invalid.org> - 2016-10-13 06:16 -0500
          Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 08:08 -0700
            Re: LDO Klaus Kragelund <klauskvik@hotmail.com> - 2016-10-13 08:57 -0700
              Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 09:05 -0700
              Re: LDO Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2016-10-13 09:26 -0700
                Re: LDO Klaus Kragelund <klauskvik@hotmail.com> - 2016-10-14 04:38 -0700
                  Re: LDO Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2016-10-14 07:42 -0700
      Re: LDO klaus.kragelund@gmail.com - 2016-10-12 14:35 -0700
        Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 15:58 -0700
        Re: LDO Robert Loos <1209@baer-gmbh.com> - 2016-10-13 08:46 +0200
      Re: LDO Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> - 2016-10-12 15:08 -0700
        Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 15:53 -0700
          Re: LDO Winfield Hill <hill@rowland.harvard.edu> - 2016-10-13 03:28 -0700
            Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 08:21 -0700
      Re: LDO piglet <erichpwagner@hotmail.com> - 2016-10-13 14:03 +0100
        Re: LDO Winfield Hill <hill@rowland.harvard.edu> - 2016-10-13 06:16 -0700
          Re: LDO piglet <erichpwagner@hotmail.com> - 2016-10-13 14:30 +0100
            Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 08:26 -0700
    Re: LDO doggerel <doggerel@nil.com> - 2016-10-12 16:07 +0800
      Re: LDO Tauno Voipio <tauno.voipio@notused.fi.invalid> - 2016-10-12 15:53 +0300
        Re: LDO doggerel <doggerel@nil.com> - 2016-10-13 10:16 +0800
      Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 07:35 -0700
        Re: LDO doggerel <doggerel@nil.com> - 2016-10-13 10:15 +0800
    Re: LDO bloggs.fredbloggs.fred@gmail.com - 2016-10-12 08:41 -0700
      Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 09:20 -0700
        Re: LDO bloggs.fredbloggs.fred@gmail.com - 2016-10-13 15:52 -0700
          Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 16:11 -0700
            Re: LDO bloggs.fredbloggs.fred@gmail.com - 2016-10-13 21:45 -0700
              Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-14 09:05 -0700
    Re: LDO Tim Wescott <tim@seemywebsite.really> - 2016-10-12 11:21 -0500
      Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 09:57 -0700
        Re: LDO Tim Wescott <tim@seemywebsite.really> - 2016-10-12 15:11 -0500
          Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-12 16:11 -0700
            Re: LDO Winfield Hill <hill@rowland.harvard.edu> - 2016-10-13 04:52 -0700
              Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 08:33 -0700
            Re: LDO Tim Wescott <seemywebsite@myfooter.really> - 2016-10-13 18:21 -0500
              Re: LDO John Larkin <jjlarkin@highlandtechnology.com> - 2016-10-13 20:15 -0700
                Re: LDO Tim Wescott <seemywebsite@myfooter.really> - 2016-10-14 12:35 -0500
            Re: LDO Tim Wescott <seemywebsite@myfooter.really> - 2016-10-13 18:24 -0500

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#431096

From	piglet <erichpwagner@hotmail.com>
Date	2016-10-13 14:30 +0100
Message-ID	<nto28m$rs8$1@dont-email.me>
In reply to	#431095

On 13/10/2016 14:16, Winfield Hill wrote:
>   Still overshoots at turnon.  Added 1nF fixes.
>
>
Very true. Could be that the final application has the 1.8V rail 
sequenced to rise after 5V is stable. But extra ref decoupling still a 
good idea.

piglet

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#431110

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-13 08:26 -0700
Message-ID	<ek9vvbhtrrov7n8kqdh4l7gecdn49pqggc@4ax.com>
In reply to	#431096

On Thu, 13 Oct 2016 14:30:09 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 13/10/2016 14:16, Winfield Hill wrote:
>>   Still overshoots at turnon.  Added 1nF fixes.
>>
>>
>Very true. Could be that the final application has the 1.8V rail 
>sequenced to rise after 5V is stable. But extra ref decoupling still a 
>good idea.
>
>piglet

I have a small forest of power supply tree. Looks like the lower
voltage switchers (3.3, 1.8, 1.0) should be powered by the 5 volt
switcher, so +5 comes up first. Switching 24 to 1.8 or 24 to 1.0 looks
dangerous; duty cycles will be a few percent and on times around 100
ns.

-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

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#430966

From	doggerel <doggerel@nil.com>
Date	2016-10-12 16:07 +0800
Message-ID	<87GdnQy1P__YcmDKnZ2dnUU7-bnNnZ2d@westnet.com.au>
In reply to	#430957

On 12-Oct-16 1:09 PM, John Larkin wrote:
>
> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
> easier to just do it from available parts than find a new regulator to
> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
> volts drain-source, the mosfet is acting like a variable resistor.
>
>
>
  SNIPPED

Novice query here.

Why is there no DC feedback path around the op amp?

If I short circuit C3 it appears to still work the same.

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#430977

From	Tauno Voipio <tauno.voipio@notused.fi.invalid>
Date	2016-10-12 15:53 +0300
Message-ID	<ntlbnm$bq9$1@dont-email.me>
In reply to	#430966

On 12.10.16 11:07, doggerel wrote:
> On 12-Oct-16 1:09 PM, John Larkin wrote:
>>
>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> easier to just do it from available parts than find a new regulator to
>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>> volts drain-source, the mosfet is acting like a variable resistor.
>>
>>
>>
>  SNIPPED
>
> Novice query here.
>
> Why is there no DC feedback path around the op amp?
>
> If I short circuit C3 it appears to still work the same.

There is: The signal OUT.

-- 

-TV

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#431069

From	doggerel <doggerel@nil.com>
Date	2016-10-13 10:16 +0800
Message-ID	<Y6-dnTopqLbsc2PKnZ2dnUU7-UdQAAAA@westnet.com.au>
In reply to	#430977

On 12-Oct-16 8:53 PM, Tauno Voipio wrote:
> On 12.10.16 11:07, doggerel wrote:
>> On 12-Oct-16 1:09 PM, John Larkin wrote:
>>>
>>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>>> easier to just do it from available parts than find a new regulator to
>>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>>> volts drain-source, the mosfet is acting like a variable resistor.
>>>
>>>
>>>
>>  SNIPPED
>>
>> Novice query here.
>>
>> Why is there no DC feedback path around the op amp?
>>
>> If I short circuit C3 it appears to still work the same.
>
> There is: The signal OUT.
>

Thanks Tauno, I missed that, pretty obvious in hindsight!

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#430988

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-12 07:35 -0700
Message-ID	<vuhsvbthc8on40cidektco3r9j147ocr0i@4ax.com>
In reply to	#430966

On Wed, 12 Oct 2016 16:07:32 +0800, doggerel <doggerel@nil.com> wrote:

>On 12-Oct-16 1:09 PM, John Larkin wrote:
>>
>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> easier to just do it from available parts than find a new regulator to
>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>> volts drain-source, the mosfet is acting like a variable resistor.
>>
>>
>>
>  SNIPPED
>
>Novice query here.
>
>Why is there no DC feedback path around the op amp?

The feedback is from OUT, which is the thing we are ultimately trying
to control.

>
>If I short circuit C3 it appears to still work the same.

Yes, but the step-load regulation isn't as good. 

Currently is a P+I (proportional + integral) control loop, which has
essentially zero DC error. Without the cap, it's a proportional-only
loop with a finite error. Having the RC in the feedback path gives
more knobs to turn too. The values were guessed, so probably need more
scientific tuning.

-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

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#431068

From	doggerel <doggerel@nil.com>
Date	2016-10-13 10:15 +0800
Message-ID	<Y6-dnTspqLbUc2PKnZ2dnUU7-UfNnZ2d@westnet.com.au>
In reply to	#430988

On 12-Oct-16 10:35 PM, John Larkin wrote:
> On Wed, 12 Oct 2016 16:07:32 +0800, doggerel <doggerel@nil.com> wrote:
>
>> On 12-Oct-16 1:09 PM, John Larkin wrote:
>>>
>>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>>> easier to just do it from available parts than find a new regulator to
>>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>>> volts drain-source, the mosfet is acting like a variable resistor.
>>>
>>>
>>>
>>  SNIPPED
>>
>> Novice query here.
>>
>> Why is there no DC feedback path around the op amp?
>
> The feedback is from OUT, which is the thing we are ultimately trying
> to control.
>
>>
>> If I short circuit C3 it appears to still work the same.
>
> Yes, but the step-load regulation isn't as good.
>
> Currently is a P+I (proportional + integral) control loop, which has
> essentially zero DC error. Without the cap, it's a proportional-only
> loop with a finite error. Having the RC in the feedback path gives
> more knobs to turn too. The values were guessed, so probably need more
> scientific tuning.
>
>
>
>
>


OK, I overlooked the 'out' net, I can see that as the P feedback and 
also the I fb via the RC network.

Thanks for the explanation its appreciated.

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#431003

From	bloggs.fredbloggs.fred@gmail.com
Date	2016-10-12 08:41 -0700
Message-ID	<a6f00047-72fb-49a3-8e9f-2c9c7505029c@googlegroups.com>
In reply to	#430957

On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
> easier to just do it from available parts than find a new regulator to
> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
> volts drain-source, the mosfet is acting like a variable resistor.
> 
> 
> 
> 
> Version 4
> SHEET 1 1080 680
> WIRE -48 -32 -144 -32
> WIRE 336 -32 256 -32
> WIRE 512 -32 336 -32
> WIRE -144 -16 -144 -32
> WIRE -48 0 -48 -32
> WIRE 512 16 512 -32
> WIRE -240 128 -272 128
> WIRE -112 128 -176 128
> WIRE 0 128 -32 128
> WIRE 256 128 256 -32
> WIRE 512 128 512 96
> WIRE -144 176 -144 64
> WIRE -432 192 -464 192
> WIRE -384 192 -432 192
> WIRE -272 192 -272 128
> WIRE -272 192 -304 192
> WIRE -176 192 -272 192
> WIRE 0 208 0 128
> WIRE 0 208 -112 208
> WIRE 48 208 0 208
> WIRE 208 208 128 208
> WIRE -176 224 -272 224
> WIRE -432 272 -464 272
> WIRE -384 272 -432 272
> WIRE -272 272 -272 224
> WIRE -272 272 -304 272
> WIRE 256 288 256 224
> WIRE 400 288 256 288
> WIRE 448 288 400 288
> WIRE 496 288 448 288
> WIRE 656 288 576 288
> WIRE 800 288 656 288
> WIRE 848 288 800 288
> WIRE 880 288 848 288
> WIRE -272 304 -272 272
> WIRE -144 304 -144 240
> WIRE 656 320 656 288
> WIRE 448 336 448 288
> WIRE 800 336 800 288
> WIRE -272 448 -272 384
> WIRE 448 464 448 400
> WIRE 656 464 656 400
> WIRE 800 464 800 416
> FLAG 448 464 0
> FLAG 400 288 OUT
> FLAG 512 128 0
> FLAG -48 0 0
> FLAG -432 192 OUT
> FLAG -272 448 0
> FLAG 800 464 0
> FLAG 656 464 0
> FLAG 848 288 LOAD
> FLAG -144 304 0
> FLAG 336 -32 1.8
> FLAG -432 272 1.8
> SYMBOL cap 432 336 R0
> WINDOW 0 -77 13 Left 2
> WINDOW 3 -79 45 Left 2
> SYMATTR InstName C2
> SYMATTR Value 47µ
> SYMBOL voltage 512 0 R0
> WINDOW 0 56 41 Left 2
> WINDOW 3 54 80 Left 2
> SYMATTR InstName V1
> SYMATTR Value 1.8
> SYMBOL Opamps\\UniversalOpamp2 -144 208 R0
> WINDOW 0 73 45 Left 2
> SYMATTR InstName U1
> SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg
> SYMBOL res 144 192 R90
> WINDOW 0 76 52 VBottom 2
> WINDOW 3 84 52 VTop 2
> SYMATTR InstName R2
> SYMATTR Value 22
> SYMBOL voltage -144 80 R180
> WINDOW 0 55 81 Left 2
> WINDOW 3 56 50 Left 2
> SYMATTR InstName V2
> SYMATTR Value 5
> SYMBOL res -288 176 R90
> WINDOW 0 -51 51 VBottom 2
> WINDOW 3 -43 53 VTop 2
> SYMATTR InstName R3
> SYMATTR Value 1K
> SYMBOL cap -176 112 R90
> WINDOW 0 0 32 VBottom 2
> WINDOW 3 32 32 VTop 2
> SYMATTR InstName C3
> SYMATTR Value 10n
> SYMBOL res -16 112 R90
> WINDOW 0 0 56 VBottom 2
> WINDOW 3 32 56 VTop 2
> SYMATTR InstName R5
> SYMATTR Value 100k
> SYMBOL current 800 336 R0
> WINDOW 3 -175 -104 Left 2
> WINDOW 123 0 0 Left 2
> WINDOW 39 0 0 Left 2
> SYMATTR Value PULSE(0 0.3 300m 0 0 100m)
> SYMATTR InstName I2
> SYMBOL res 480 304 R270
> WINDOW 0 82 55 VTop 2
> WINDOW 3 73 55 VBottom 2
> SYMATTR InstName R6
> SYMATTR Value 1m
> SYMBOL nmos 208 128 R0
> WINDOW 0 124 30 Left 2
> WINDOW 3 85 72 Left 2
> SYMATTR InstName M1
> SYMATTR Value NTLMS4504N
> SYMBOL res 640 304 R0
> WINDOW 0 -63 62 Left 2
> WINDOW 3 -59 97 Left 2
> SYMATTR InstName R1
> SYMATTR Value 10
> SYMBOL res -288 288 R0
> WINDOW 0 52 74 Left 2
> WINDOW 3 51 107 Left 2
> SYMATTR InstName R4
> SYMATTR Value 5K
> SYMBOL res -288 256 R90
> WINDOW 0 70 62 VBottom 2
> WINDOW 3 76 63 VTop 2
> SYMATTR InstName R7
> SYMATTR Value 1K
> TEXT 696 112 Left 2 !.tran 500m uic
> TEXT 696 0 Left 2 ;1.8 to 1.5 LDO
> TEXT 688 48 Left 2 ;JL  Oct 11, 2016
> TEXT 104 72 Left 2 ;IRLM6344
> TEXT 120 112 Left 2 ;SOT23
> TEXT -96 288 Left 2 ;NCS2005
> TEXT -96 320 Left 2 ;SOT23
> TEXT 344 416 Left 2 ;1206

Is there something novel here? I'm missing it.

> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

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#431009

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-12 09:20 -0700
Message-ID	<1kosvbl46o6t5r39vvu5llgr86pei794m3@4ax.com>
In reply to	#431003

On Wed, 12 Oct 2016 08:41:39 -0700 (PDT),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> easier to just do it from available parts than find a new regulator to
>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>> volts drain-source, the mosfet is acting like a variable resistor.
>> 
>> 
>> 
>> 
>> Version 4
>> SHEET 1 1080 680
>> WIRE -48 -32 -144 -32
>> WIRE 336 -32 256 -32
>> WIRE 512 -32 336 -32
>> WIRE -144 -16 -144 -32
>> WIRE -48 0 -48 -32
>> WIRE 512 16 512 -32
>> WIRE -240 128 -272 128
>> WIRE -112 128 -176 128
>> WIRE 0 128 -32 128
>> WIRE 256 128 256 -32
>> WIRE 512 128 512 96
>> WIRE -144 176 -144 64
>> WIRE -432 192 -464 192
>> WIRE -384 192 -432 192
>> WIRE -272 192 -272 128
>> WIRE -272 192 -304 192
>> WIRE -176 192 -272 192
>> WIRE 0 208 0 128
>> WIRE 0 208 -112 208
>> WIRE 48 208 0 208
>> WIRE 208 208 128 208
>> WIRE -176 224 -272 224
>> WIRE -432 272 -464 272
>> WIRE -384 272 -432 272
>> WIRE -272 272 -272 224
>> WIRE -272 272 -304 272
>> WIRE 256 288 256 224
>> WIRE 400 288 256 288
>> WIRE 448 288 400 288
>> WIRE 496 288 448 288
>> WIRE 656 288 576 288
>> WIRE 800 288 656 288
>> WIRE 848 288 800 288
>> WIRE 880 288 848 288
>> WIRE -272 304 -272 272
>> WIRE -144 304 -144 240
>> WIRE 656 320 656 288
>> WIRE 448 336 448 288
>> WIRE 800 336 800 288
>> WIRE -272 448 -272 384
>> WIRE 448 464 448 400
>> WIRE 656 464 656 400
>> WIRE 800 464 800 416
>> FLAG 448 464 0
>> FLAG 400 288 OUT
>> FLAG 512 128 0
>> FLAG -48 0 0
>> FLAG -432 192 OUT
>> FLAG -272 448 0
>> FLAG 800 464 0
>> FLAG 656 464 0
>> FLAG 848 288 LOAD
>> FLAG -144 304 0
>> FLAG 336 -32 1.8
>> FLAG -432 272 1.8
>> SYMBOL cap 432 336 R0
>> WINDOW 0 -77 13 Left 2
>> WINDOW 3 -79 45 Left 2
>> SYMATTR InstName C2
>> SYMATTR Value 47µ
>> SYMBOL voltage 512 0 R0
>> WINDOW 0 56 41 Left 2
>> WINDOW 3 54 80 Left 2
>> SYMATTR InstName V1
>> SYMATTR Value 1.8
>> SYMBOL Opamps\\UniversalOpamp2 -144 208 R0
>> WINDOW 0 73 45 Left 2
>> SYMATTR InstName U1
>> SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg
>> SYMBOL res 144 192 R90
>> WINDOW 0 76 52 VBottom 2
>> WINDOW 3 84 52 VTop 2
>> SYMATTR InstName R2
>> SYMATTR Value 22
>> SYMBOL voltage -144 80 R180
>> WINDOW 0 55 81 Left 2
>> WINDOW 3 56 50 Left 2
>> SYMATTR InstName V2
>> SYMATTR Value 5
>> SYMBOL res -288 176 R90
>> WINDOW 0 -51 51 VBottom 2
>> WINDOW 3 -43 53 VTop 2
>> SYMATTR InstName R3
>> SYMATTR Value 1K
>> SYMBOL cap -176 112 R90
>> WINDOW 0 0 32 VBottom 2
>> WINDOW 3 32 32 VTop 2
>> SYMATTR InstName C3
>> SYMATTR Value 10n
>> SYMBOL res -16 112 R90
>> WINDOW 0 0 56 VBottom 2
>> WINDOW 3 32 56 VTop 2
>> SYMATTR InstName R5
>> SYMATTR Value 100k
>> SYMBOL current 800 336 R0
>> WINDOW 3 -175 -104 Left 2
>> WINDOW 123 0 0 Left 2
>> WINDOW 39 0 0 Left 2
>> SYMATTR Value PULSE(0 0.3 300m 0 0 100m)
>> SYMATTR InstName I2
>> SYMBOL res 480 304 R270
>> WINDOW 0 82 55 VTop 2
>> WINDOW 3 73 55 VBottom 2
>> SYMATTR InstName R6
>> SYMATTR Value 1m
>> SYMBOL nmos 208 128 R0
>> WINDOW 0 124 30 Left 2
>> WINDOW 3 85 72 Left 2
>> SYMATTR InstName M1
>> SYMATTR Value NTLMS4504N
>> SYMBOL res 640 304 R0
>> WINDOW 0 -63 62 Left 2
>> WINDOW 3 -59 97 Left 2
>> SYMATTR InstName R1
>> SYMATTR Value 10
>> SYMBOL res -288 288 R0
>> WINDOW 0 52 74 Left 2
>> WINDOW 3 51 107 Left 2
>> SYMATTR InstName R4
>> SYMATTR Value 5K
>> SYMBOL res -288 256 R90
>> WINDOW 0 70 62 VBottom 2
>> WINDOW 3 76 63 VTop 2
>> SYMATTR InstName R7
>> SYMATTR Value 1K
>> TEXT 696 112 Left 2 !.tran 500m uic
>> TEXT 696 0 Left 2 ;1.8 to 1.5 LDO
>> TEXT 688 48 Left 2 ;JL  Oct 11, 2016
>> TEXT 104 72 Left 2 ;IRLM6344
>> TEXT 120 112 Left 2 ;SOT23
>> TEXT -96 288 Left 2 ;NCS2005
>> TEXT -96 320 Left 2 ;SOT23
>> TEXT 344 416 Left 2 ;1206
>
>Is there something novel here? I'm missing it.
>

Just a 0.3 volt LDO, using a mosfet in ohmic mode.

Why don't you post a more interesting circuit?


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

[toc] | [prev] | [next] | [standalone]

#431156

From	bloggs.fredbloggs.fred@gmail.com
Date	2016-10-13 15:52 -0700
Message-ID	<770a169b-be00-47ce-95d5-5a567320d43e@googlegroups.com>
In reply to	#431009

On Wednesday, October 12, 2016 at 12:20:25 PM UTC-4, John Larkin wrote:
> On Wed, 12 Oct 2016 08:41:39 -0700 (PDT),
> bloggs.fredbloggs.fred@gmail.com wrote:
> 
> >On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
> >> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
> >> easier to just do it from available parts than find a new regulator to
> >> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
> >> volts drain-source, the mosfet is acting like a variable resistor.
> >> 
> >> 
> >> 
> >> 
> >> Version 4
> >> SHEET 1 1080 680
> >> WIRE -48 -32 -144 -32
> >> WIRE 336 -32 256 -32
> >> WIRE 512 -32 336 -32
> >> WIRE -144 -16 -144 -32
> >> WIRE -48 0 -48 -32
> >> WIRE 512 16 512 -32
> >> WIRE -240 128 -272 128
> >> WIRE -112 128 -176 128
> >> WIRE 0 128 -32 128
> >> WIRE 256 128 256 -32
> >> WIRE 512 128 512 96
> >> WIRE -144 176 -144 64
> >> WIRE -432 192 -464 192
> >> WIRE -384 192 -432 192
> >> WIRE -272 192 -272 128
> >> WIRE -272 192 -304 192
> >> WIRE -176 192 -272 192
> >> WIRE 0 208 0 128
> >> WIRE 0 208 -112 208
> >> WIRE 48 208 0 208
> >> WIRE 208 208 128 208
> >> WIRE -176 224 -272 224
> >> WIRE -432 272 -464 272
> >> WIRE -384 272 -432 272
> >> WIRE -272 272 -272 224
> >> WIRE -272 272 -304 272
> >> WIRE 256 288 256 224
> >> WIRE 400 288 256 288
> >> WIRE 448 288 400 288
> >> WIRE 496 288 448 288
> >> WIRE 656 288 576 288
> >> WIRE 800 288 656 288
> >> WIRE 848 288 800 288
> >> WIRE 880 288 848 288
> >> WIRE -272 304 -272 272
> >> WIRE -144 304 -144 240
> >> WIRE 656 320 656 288
> >> WIRE 448 336 448 288
> >> WIRE 800 336 800 288
> >> WIRE -272 448 -272 384
> >> WIRE 448 464 448 400
> >> WIRE 656 464 656 400
> >> WIRE 800 464 800 416
> >> FLAG 448 464 0
> >> FLAG 400 288 OUT
> >> FLAG 512 128 0
> >> FLAG -48 0 0
> >> FLAG -432 192 OUT
> >> FLAG -272 448 0
> >> FLAG 800 464 0
> >> FLAG 656 464 0
> >> FLAG 848 288 LOAD
> >> FLAG -144 304 0
> >> FLAG 336 -32 1.8
> >> FLAG -432 272 1.8
> >> SYMBOL cap 432 336 R0
> >> WINDOW 0 -77 13 Left 2
> >> WINDOW 3 -79 45 Left 2
> >> SYMATTR InstName C2
> >> SYMATTR Value 47µ
> >> SYMBOL voltage 512 0 R0
> >> WINDOW 0 56 41 Left 2
> >> WINDOW 3 54 80 Left 2
> >> SYMATTR InstName V1
> >> SYMATTR Value 1.8
> >> SYMBOL Opamps\\UniversalOpamp2 -144 208 R0
> >> WINDOW 0 73 45 Left 2
> >> SYMATTR InstName U1
> >> SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg
> >> SYMBOL res 144 192 R90
> >> WINDOW 0 76 52 VBottom 2
> >> WINDOW 3 84 52 VTop 2
> >> SYMATTR InstName R2
> >> SYMATTR Value 22
> >> SYMBOL voltage -144 80 R180
> >> WINDOW 0 55 81 Left 2
> >> WINDOW 3 56 50 Left 2
> >> SYMATTR InstName V2
> >> SYMATTR Value 5
> >> SYMBOL res -288 176 R90
> >> WINDOW 0 -51 51 VBottom 2
> >> WINDOW 3 -43 53 VTop 2
> >> SYMATTR InstName R3
> >> SYMATTR Value 1K
> >> SYMBOL cap -176 112 R90
> >> WINDOW 0 0 32 VBottom 2
> >> WINDOW 3 32 32 VTop 2
> >> SYMATTR InstName C3
> >> SYMATTR Value 10n
> >> SYMBOL res -16 112 R90
> >> WINDOW 0 0 56 VBottom 2
> >> WINDOW 3 32 56 VTop 2
> >> SYMATTR InstName R5
> >> SYMATTR Value 100k
> >> SYMBOL current 800 336 R0
> >> WINDOW 3 -175 -104 Left 2
> >> WINDOW 123 0 0 Left 2
> >> WINDOW 39 0 0 Left 2
> >> SYMATTR Value PULSE(0 0.3 300m 0 0 100m)
> >> SYMATTR InstName I2
> >> SYMBOL res 480 304 R270
> >> WINDOW 0 82 55 VTop 2
> >> WINDOW 3 73 55 VBottom 2
> >> SYMATTR InstName R6
> >> SYMATTR Value 1m
> >> SYMBOL nmos 208 128 R0
> >> WINDOW 0 124 30 Left 2
> >> WINDOW 3 85 72 Left 2
> >> SYMATTR InstName M1
> >> SYMATTR Value NTLMS4504N
> >> SYMBOL res 640 304 R0
> >> WINDOW 0 -63 62 Left 2
> >> WINDOW 3 -59 97 Left 2
> >> SYMATTR InstName R1
> >> SYMATTR Value 10
> >> SYMBOL res -288 288 R0
> >> WINDOW 0 52 74 Left 2
> >> WINDOW 3 51 107 Left 2
> >> SYMATTR InstName R4
> >> SYMATTR Value 5K
> >> SYMBOL res -288 256 R90
> >> WINDOW 0 70 62 VBottom 2
> >> WINDOW 3 76 63 VTop 2
> >> SYMATTR InstName R7
> >> SYMATTR Value 1K
> >> TEXT 696 112 Left 2 !.tran 500m uic
> >> TEXT 696 0 Left 2 ;1.8 to 1.5 LDO
> >> TEXT 688 48 Left 2 ;JL  Oct 11, 2016
> >> TEXT 104 72 Left 2 ;IRLM6344
> >> TEXT 120 112 Left 2 ;SOT23
> >> TEXT -96 288 Left 2 ;NCS2005
> >> TEXT -96 320 Left 2 ;SOT23
> >> TEXT 344 416 Left 2 ;1206
> >
> >Is there something novel here? I'm missing it.
> >
> 
> Just a 0.3 volt LDO, using a mosfet in ohmic mode.
> 
> Why don't you post a more interesting circuit?
> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

I have no idea what a DDR3 RAM is but looks like there're lots of high efficiency very compact minimal component count microminiaturized switching solutions, so who in there right mind would use a bunch of parts to make an analog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.

[toc] | [prev] | [next] | [standalone]

#431158

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-13 16:11 -0700
Message-ID	<bd400ch79rrhffjph6eud2jik9pk9nnp3n@4ax.com>
In reply to	#431156

On Thu, 13 Oct 2016 15:52:48 -0700 (PDT),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Wednesday, October 12, 2016 at 12:20:25 PM UTC-4, John Larkin wrote:
>> On Wed, 12 Oct 2016 08:41:39 -0700 (PDT),
>> bloggs.fredbloggs.fred@gmail.com wrote:
>> 
>> >On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
>> >> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> >> easier to just do it from available parts than find a new regulator to
>> >> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>> >> volts drain-source, the mosfet is acting like a variable resistor.
>> >> 
>> >> 
>> >> 
>> >> 
>> >> Version 4
>> >> SHEET 1 1080 680
>> >> WIRE -48 -32 -144 -32
>> >> WIRE 336 -32 256 -32
>> >> WIRE 512 -32 336 -32
>> >> WIRE -144 -16 -144 -32
>> >> WIRE -48 0 -48 -32
>> >> WIRE 512 16 512 -32
>> >> WIRE -240 128 -272 128
>> >> WIRE -112 128 -176 128
>> >> WIRE 0 128 -32 128
>> >> WIRE 256 128 256 -32
>> >> WIRE 512 128 512 96
>> >> WIRE -144 176 -144 64
>> >> WIRE -432 192 -464 192
>> >> WIRE -384 192 -432 192
>> >> WIRE -272 192 -272 128
>> >> WIRE -272 192 -304 192
>> >> WIRE -176 192 -272 192
>> >> WIRE 0 208 0 128
>> >> WIRE 0 208 -112 208
>> >> WIRE 48 208 0 208
>> >> WIRE 208 208 128 208
>> >> WIRE -176 224 -272 224
>> >> WIRE -432 272 -464 272
>> >> WIRE -384 272 -432 272
>> >> WIRE -272 272 -272 224
>> >> WIRE -272 272 -304 272
>> >> WIRE 256 288 256 224
>> >> WIRE 400 288 256 288
>> >> WIRE 448 288 400 288
>> >> WIRE 496 288 448 288
>> >> WIRE 656 288 576 288
>> >> WIRE 800 288 656 288
>> >> WIRE 848 288 800 288
>> >> WIRE 880 288 848 288
>> >> WIRE -272 304 -272 272
>> >> WIRE -144 304 -144 240
>> >> WIRE 656 320 656 288
>> >> WIRE 448 336 448 288
>> >> WIRE 800 336 800 288
>> >> WIRE -272 448 -272 384
>> >> WIRE 448 464 448 400
>> >> WIRE 656 464 656 400
>> >> WIRE 800 464 800 416
>> >> FLAG 448 464 0
>> >> FLAG 400 288 OUT
>> >> FLAG 512 128 0
>> >> FLAG -48 0 0
>> >> FLAG -432 192 OUT
>> >> FLAG -272 448 0
>> >> FLAG 800 464 0
>> >> FLAG 656 464 0
>> >> FLAG 848 288 LOAD
>> >> FLAG -144 304 0
>> >> FLAG 336 -32 1.8
>> >> FLAG -432 272 1.8
>> >> SYMBOL cap 432 336 R0
>> >> WINDOW 0 -77 13 Left 2
>> >> WINDOW 3 -79 45 Left 2
>> >> SYMATTR InstName C2
>> >> SYMATTR Value 47µ
>> >> SYMBOL voltage 512 0 R0
>> >> WINDOW 0 56 41 Left 2
>> >> WINDOW 3 54 80 Left 2
>> >> SYMATTR InstName V1
>> >> SYMATTR Value 1.8
>> >> SYMBOL Opamps\\UniversalOpamp2 -144 208 R0
>> >> WINDOW 0 73 45 Left 2
>> >> SYMATTR InstName U1
>> >> SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg
>> >> SYMBOL res 144 192 R90
>> >> WINDOW 0 76 52 VBottom 2
>> >> WINDOW 3 84 52 VTop 2
>> >> SYMATTR InstName R2
>> >> SYMATTR Value 22
>> >> SYMBOL voltage -144 80 R180
>> >> WINDOW 0 55 81 Left 2
>> >> WINDOW 3 56 50 Left 2
>> >> SYMATTR InstName V2
>> >> SYMATTR Value 5
>> >> SYMBOL res -288 176 R90
>> >> WINDOW 0 -51 51 VBottom 2
>> >> WINDOW 3 -43 53 VTop 2
>> >> SYMATTR InstName R3
>> >> SYMATTR Value 1K
>> >> SYMBOL cap -176 112 R90
>> >> WINDOW 0 0 32 VBottom 2
>> >> WINDOW 3 32 32 VTop 2
>> >> SYMATTR InstName C3
>> >> SYMATTR Value 10n
>> >> SYMBOL res -16 112 R90
>> >> WINDOW 0 0 56 VBottom 2
>> >> WINDOW 3 32 56 VTop 2
>> >> SYMATTR InstName R5
>> >> SYMATTR Value 100k
>> >> SYMBOL current 800 336 R0
>> >> WINDOW 3 -175 -104 Left 2
>> >> WINDOW 123 0 0 Left 2
>> >> WINDOW 39 0 0 Left 2
>> >> SYMATTR Value PULSE(0 0.3 300m 0 0 100m)
>> >> SYMATTR InstName I2
>> >> SYMBOL res 480 304 R270
>> >> WINDOW 0 82 55 VTop 2
>> >> WINDOW 3 73 55 VBottom 2
>> >> SYMATTR InstName R6
>> >> SYMATTR Value 1m
>> >> SYMBOL nmos 208 128 R0
>> >> WINDOW 0 124 30 Left 2
>> >> WINDOW 3 85 72 Left 2
>> >> SYMATTR InstName M1
>> >> SYMATTR Value NTLMS4504N
>> >> SYMBOL res 640 304 R0
>> >> WINDOW 0 -63 62 Left 2
>> >> WINDOW 3 -59 97 Left 2
>> >> SYMATTR InstName R1
>> >> SYMATTR Value 10
>> >> SYMBOL res -288 288 R0
>> >> WINDOW 0 52 74 Left 2
>> >> WINDOW 3 51 107 Left 2
>> >> SYMATTR InstName R4
>> >> SYMATTR Value 5K
>> >> SYMBOL res -288 256 R90
>> >> WINDOW 0 70 62 VBottom 2
>> >> WINDOW 3 76 63 VTop 2
>> >> SYMATTR InstName R7
>> >> SYMATTR Value 1K
>> >> TEXT 696 112 Left 2 !.tran 500m uic
>> >> TEXT 696 0 Left 2 ;1.8 to 1.5 LDO
>> >> TEXT 688 48 Left 2 ;JL  Oct 11, 2016
>> >> TEXT 104 72 Left 2 ;IRLM6344
>> >> TEXT 120 112 Left 2 ;SOT23
>> >> TEXT -96 288 Left 2 ;NCS2005
>> >> TEXT -96 320 Left 2 ;SOT23
>> >> TEXT 344 416 Left 2 ;1206
>> >
>> >Is there something novel here? I'm missing it.
>> >
>> 
>> Just a 0.3 volt LDO, using a mosfet in ohmic mode.
>> 
>> Why don't you post a more interesting circuit?
>> 
>> 
>> -- 
>> 
>> John Larkin         Highland Technology, Inc
>> 
>> lunatic fringe electronics
>
>I have no idea what a DDR3 RAM is but looks like there're lots of high efficiency very compact minimal component count microminiaturized switching solutions, so who in there right mind would use a bunch of parts to make an analog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.

I'm already switching 24 down to 1.8 (for the FPGA aux supply) so this
is a sensible way to make 1.5. The "bunch of parts" is a pretty small
bunch.

DDR3 is a category of fast (double data rate, which means using both
clock edges to move data) dynamic RAM. I think most computers use DDR3
(or DDR4?) ram nowadays.

https://en.wikipedia.org/wiki/DDR3_SDRAM


The dram controller in the FPGA actually experimentally calibrates and
compensates for the delay of all the data lines. Timing is tight.


-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#431178

From	bloggs.fredbloggs.fred@gmail.com
Date	2016-10-13 21:45 -0700
Message-ID	<c3fa1c8e-dc5d-4369-b70b-7c31249e4d23@googlegroups.com>
In reply to	#431158

On Thursday, October 13, 2016 at 7:11:47 PM UTC-4, John Larkin wrote:
> On Thu, 13 Oct 2016 15:52:48 -0700 (PDT),
> bloggs.fredbloggs.fred@gmail.com wrote:
> 
> >On Wednesday, October 12, 2016 at 12:20:25 PM UTC-4, John Larkin wrote:
> >> On Wed, 12 Oct 2016 08:41:39 -0700 (PDT),
> >> bloggs.fredbloggs.fred@gmail.com wrote:
> >> 
> >> >On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
> >> >> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
> >> >> easier to just do it from available parts than find a new regulator to
> >> >> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
> >> >> volts drain-source, the mosfet is acting like a variable resistor.
> >> >> 
> >> >> 
> >> >> 
> >> >> 
> >> >> Version 4
> >> >> SHEET 1 1080 680
> >> >> WIRE -48 -32 -144 -32
> >> >> WIRE 336 -32 256 -32
> >> >> WIRE 512 -32 336 -32
> >> >> WIRE -144 -16 -144 -32
> >> >> WIRE -48 0 -48 -32
> >> >> WIRE 512 16 512 -32
> >> >> WIRE -240 128 -272 128
> >> >> WIRE -112 128 -176 128
> >> >> WIRE 0 128 -32 128
> >> >> WIRE 256 128 256 -32
> >> >> WIRE 512 128 512 96
> >> >> WIRE -144 176 -144 64
> >> >> WIRE -432 192 -464 192
> >> >> WIRE -384 192 -432 192
> >> >> WIRE -272 192 -272 128
> >> >> WIRE -272 192 -304 192
> >> >> WIRE -176 192 -272 192
> >> >> WIRE 0 208 0 128
> >> >> WIRE 0 208 -112 208
> >> >> WIRE 48 208 0 208
> >> >> WIRE 208 208 128 208
> >> >> WIRE -176 224 -272 224
> >> >> WIRE -432 272 -464 272
> >> >> WIRE -384 272 -432 272
> >> >> WIRE -272 272 -272 224
> >> >> WIRE -272 272 -304 272
> >> >> WIRE 256 288 256 224
> >> >> WIRE 400 288 256 288
> >> >> WIRE 448 288 400 288
> >> >> WIRE 496 288 448 288
> >> >> WIRE 656 288 576 288
> >> >> WIRE 800 288 656 288
> >> >> WIRE 848 288 800 288
> >> >> WIRE 880 288 848 288
> >> >> WIRE -272 304 -272 272
> >> >> WIRE -144 304 -144 240
> >> >> WIRE 656 320 656 288
> >> >> WIRE 448 336 448 288
> >> >> WIRE 800 336 800 288
> >> >> WIRE -272 448 -272 384
> >> >> WIRE 448 464 448 400
> >> >> WIRE 656 464 656 400
> >> >> WIRE 800 464 800 416
> >> >> FLAG 448 464 0
> >> >> FLAG 400 288 OUT
> >> >> FLAG 512 128 0
> >> >> FLAG -48 0 0
> >> >> FLAG -432 192 OUT
> >> >> FLAG -272 448 0
> >> >> FLAG 800 464 0
> >> >> FLAG 656 464 0
> >> >> FLAG 848 288 LOAD
> >> >> FLAG -144 304 0
> >> >> FLAG 336 -32 1.8
> >> >> FLAG -432 272 1.8
> >> >> SYMBOL cap 432 336 R0
> >> >> WINDOW 0 -77 13 Left 2
> >> >> WINDOW 3 -79 45 Left 2
> >> >> SYMATTR InstName C2
> >> >> SYMATTR Value 47µ
> >> >> SYMBOL voltage 512 0 R0
> >> >> WINDOW 0 56 41 Left 2
> >> >> WINDOW 3 54 80 Left 2
> >> >> SYMATTR InstName V1
> >> >> SYMATTR Value 1.8
> >> >> SYMBOL Opamps\\UniversalOpamp2 -144 208 R0
> >> >> WINDOW 0 73 45 Left 2
> >> >> SYMATTR InstName U1
> >> >> SYMATTR Value2 Avol=1Meg GBW=8Meg Slew=10Meg
> >> >> SYMBOL res 144 192 R90
> >> >> WINDOW 0 76 52 VBottom 2
> >> >> WINDOW 3 84 52 VTop 2
> >> >> SYMATTR InstName R2
> >> >> SYMATTR Value 22
> >> >> SYMBOL voltage -144 80 R180
> >> >> WINDOW 0 55 81 Left 2
> >> >> WINDOW 3 56 50 Left 2
> >> >> SYMATTR InstName V2
> >> >> SYMATTR Value 5
> >> >> SYMBOL res -288 176 R90
> >> >> WINDOW 0 -51 51 VBottom 2
> >> >> WINDOW 3 -43 53 VTop 2
> >> >> SYMATTR InstName R3
> >> >> SYMATTR Value 1K
> >> >> SYMBOL cap -176 112 R90
> >> >> WINDOW 0 0 32 VBottom 2
> >> >> WINDOW 3 32 32 VTop 2
> >> >> SYMATTR InstName C3
> >> >> SYMATTR Value 10n
> >> >> SYMBOL res -16 112 R90
> >> >> WINDOW 0 0 56 VBottom 2
> >> >> WINDOW 3 32 56 VTop 2
> >> >> SYMATTR InstName R5
> >> >> SYMATTR Value 100k
> >> >> SYMBOL current 800 336 R0
> >> >> WINDOW 3 -175 -104 Left 2
> >> >> WINDOW 123 0 0 Left 2
> >> >> WINDOW 39 0 0 Left 2
> >> >> SYMATTR Value PULSE(0 0.3 300m 0 0 100m)
> >> >> SYMATTR InstName I2
> >> >> SYMBOL res 480 304 R270
> >> >> WINDOW 0 82 55 VTop 2
> >> >> WINDOW 3 73 55 VBottom 2
> >> >> SYMATTR InstName R6
> >> >> SYMATTR Value 1m
> >> >> SYMBOL nmos 208 128 R0
> >> >> WINDOW 0 124 30 Left 2
> >> >> WINDOW 3 85 72 Left 2
> >> >> SYMATTR InstName M1
> >> >> SYMATTR Value NTLMS4504N
> >> >> SYMBOL res 640 304 R0
> >> >> WINDOW 0 -63 62 Left 2
> >> >> WINDOW 3 -59 97 Left 2
> >> >> SYMATTR InstName R1
> >> >> SYMATTR Value 10
> >> >> SYMBOL res -288 288 R0
> >> >> WINDOW 0 52 74 Left 2
> >> >> WINDOW 3 51 107 Left 2
> >> >> SYMATTR InstName R4
> >> >> SYMATTR Value 5K
> >> >> SYMBOL res -288 256 R90
> >> >> WINDOW 0 70 62 VBottom 2
> >> >> WINDOW 3 76 63 VTop 2
> >> >> SYMATTR InstName R7
> >> >> SYMATTR Value 1K
> >> >> TEXT 696 112 Left 2 !.tran 500m uic
> >> >> TEXT 696 0 Left 2 ;1.8 to 1.5 LDO
> >> >> TEXT 688 48 Left 2 ;JL  Oct 11, 2016
> >> >> TEXT 104 72 Left 2 ;IRLM6344
> >> >> TEXT 120 112 Left 2 ;SOT23
> >> >> TEXT -96 288 Left 2 ;NCS2005
> >> >> TEXT -96 320 Left 2 ;SOT23
> >> >> TEXT 344 416 Left 2 ;1206
> >> >
> >> >Is there something novel here? I'm missing it.
> >> >
> >> 
> >> Just a 0.3 volt LDO, using a mosfet in ohmic mode.
> >> 
> >> Why don't you post a more interesting circuit?
> >> 
> >> 
> >> -- 
> >> 
> >> John Larkin         Highland Technology, Inc
> >> 
> >> lunatic fringe electronics
> >
> >I have no idea what a DDR3 RAM is but looks like there're lots of high efficiency very compact minimal component count microminiaturized switching solutions, so who in there right mind would use a bunch of parts to make an analog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.
> 
> I'm already switching 24 down to 1.8 (for the FPGA aux supply) so this
> is a sensible way to make 1.5. The "bunch of parts" is a pretty small
> bunch.
> 
> DDR3 is a category of fast (double data rate, which means using both
> clock edges to move data) dynamic RAM. I think most computers use DDR3
> (or DDR4?) ram nowadays.
> 
> https://en.wikipedia.org/wiki/DDR3_SDRAM
> 
> 
> The dram controller in the FPGA actually experimentally calibrates and
> compensates for the delay of all the data lines. Timing is tight.

Okay, thanks for the explanation. You have a ton of parts and headache compared to something like this http://www.linear.com/product/LTC3541-2 , which is more of a battery powered system part but does show the kinds of savings available.


> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> picosecond timing   precision measurement 
> 
> jlarkin att highlandtechnology dott com
> http://www.highlandtechnology.com

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#431215

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-14 09:05 -0700
Message-ID	<89020cd3rti4homigqmnsnfjegtlet7o8o@4ax.com>
In reply to	#431178

On Thu, 13 Oct 2016 21:45:46 -0700 (PDT),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Thursday, October 13, 2016 at 7:11:47 PM UTC-4, John Larkin wrote:
>> On Thu, 13 Oct 2016 15:52:48 -0700 (PDT),
>> bloggs.fredbloggs.fred@gmail.com wrote:
>> 
>> >On Wednesday, October 12, 2016 at 12:20:25 PM UTC-4, John Larkin wrote:
>> >> On Wed, 12 Oct 2016 08:41:39 -0700 (PDT),
>> >> bloggs.fredbloggs.fred@gmail.com wrote:
>> >> 
>> >> >On Wednesday, October 12, 2016 at 1:10:08 AM UTC-4, John Larkin wrote:
>> >> >> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> >> >> easier to just do it from available parts than find a new regulator to
>> >> >> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>> >> >> volts drain-source, the mosfet is acting like a variable resistor.
>> >> >> 
>> >> >> 
>> >> >> 

>> >
>> >I have no idea what a DDR3 RAM is but looks like there're lots of high efficiency very compact minimal component count microminiaturized switching solutions, so who in there right mind would use a bunch of parts to make an analog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.
>> 
>> I'm already switching 24 down to 1.8 (for the FPGA aux supply) so this
>> is a sensible way to make 1.5. The "bunch of parts" is a pretty small
>> bunch.
>> 
>> DDR3 is a category of fast (double data rate, which means using both
>> clock edges to move data) dynamic RAM. I think most computers use DDR3
>> (or DDR4?) ram nowadays.
>> 
>> https://en.wikipedia.org/wiki/DDR3_SDRAM
>> 
>> 
>> The dram controller in the FPGA actually experimentally calibrates and
>> compensates for the delay of all the data lines. Timing is tight.
>
>Okay, thanks for the explanation. You have a ton of parts and headache compared to something like this http://www.linear.com/product/LTC3541-2 , which is more of a battery powered system part but does show the kinds of savings available.
>
>

I just got an eval board for the Linear LT8602, which is a cute quad
synchronous switcher. It seems to work fine. It's interesting that
they intend two of the outputs to run off the prime DC source, and two
others to run off one of the switcher outputs.

My production people dislike QFN leadless packages, so the TI TPS54302
is still appealing.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

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#431010

From	Tim Wescott <tim@seemywebsite.really>
Date	2016-10-12 11:21 -0500
Message-ID	<K5ednXGmuP6A_mPKnZ2dnUU7-c2dnZ2d@giganews.com>
In reply to	#430957

On Tue, 11 Oct 2016 22:09:59 -0700, John Larkin wrote:

> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
> easier to just do it from available parts than find a new regulator to
> buy. Loop comp is the first wild guess, but it looks fine. At 0.3 volts
> drain-source, the mosfet is acting like a variable resistor.
> 
Don't have time to put this on LT Spice, but do an AC analysis of the 
input and output impedances when it's running at design current and maybe 
2x and 1/2 as much.  Look for where the real part goes negative, and 
consider whether that's going to find fertile ground for oscillation.

(If you've got power gain and more than 180 degrees of phase shift, 
you're pretty much guaranteed that the output impedance will go negative 
at some frequency.)

To sweep for an impedance shove a voltage or current source in there 
someplace (or use an existing one).  Set the DC value to zero (or use 
what you had been for your simulation), set the AC value to 1, run the 
sweep, and plot the current or voltage vs. frequency.  The admittance (or 
impedance) jumps right out at you.

-- 
www.wescottdesign.com

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#431015

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-12 09:57 -0700
Message-ID	<u4qsvbp936mb9vjhnfk1tcob5eu7vv5bn2@4ax.com>
In reply to	#431010

On Wed, 12 Oct 2016 11:21:49 -0500, Tim Wescott
<tim@seemywebsite.really> wrote:

>On Tue, 11 Oct 2016 22:09:59 -0700, John Larkin wrote:
>
>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>> easier to just do it from available parts than find a new regulator to
>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3 volts
>> drain-source, the mosfet is acting like a variable resistor.
>> 
>Don't have time to put this on LT Spice, but do an AC analysis of the 
>input and output impedances when it's running at design current and maybe 
>2x and 1/2 as much.  Look for where the real part goes negative, and 
>consider whether that's going to find fertile ground for oscillation.

The transfer curve of the fet is very nonlinear, and it's acting like
a variable resistor, so the output time constant is continuously
changing. I wouldn't want to try to write closed-form equations for
the load-step response, or to evaluate stability over the load range.
This is clearly a case where Spice wins.

The loop is unnecessarily hot, but was a first guess. It needs
tweaking. What's important is to design a circuit that can be tweaked.

The LDO is powering a 4 gbit DDR3 ram and the FPGA bank that
interfaces it. I have no good estimate of either the active or the
idle current, or the time profile of the load current. The big output
cap helps a lot here. I may need a dump resistor (R1) but probably
not; gotta research the FPGA and the dram to be sure. The output can't
go up much, given there's only 1.8 volts available.

>
>(If you've got power gain and more than 180 degrees of phase shift, 
>you're pretty much guaranteed that the output impedance will go negative 
>at some frequency.)

Simulated load steps are a great way to estimate, well, load step
response. Ringing suggests low phase margins.

>
>To sweep for an impedance shove a voltage or current source in there 
>someplace (or use an existing one).  Set the DC value to zero (or use 
>what you had been for your simulation), set the AC value to 1, run the 
>sweep, and plot the current or voltage vs. frequency.  The admittance (or 
>impedance) jumps right out at you.

Load steps do that, in the time domain. But they account for the large
nonlinearities, which AC analysis doesn't.

-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

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#431032

From	Tim Wescott <tim@seemywebsite.really>
Date	2016-10-12 15:11 -0500
Message-ID	<krWdnRBkJdBqBWPKnZ2dnUU7-LednZ2d@giganews.com>
In reply to	#431015

On Wed, 12 Oct 2016 09:57:17 -0700, John Larkin wrote:

> On Wed, 12 Oct 2016 11:21:49 -0500, Tim Wescott
> <tim@seemywebsite.really> wrote:
> 
>>On Tue, 11 Oct 2016 22:09:59 -0700, John Larkin wrote:
>>
>>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>>> easier to just do it from available parts than find a new regulator to
>>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>>> volts drain-source, the mosfet is acting like a variable resistor.
>>> 
>>Don't have time to put this on LT Spice, but do an AC analysis of the
>>input and output impedances when it's running at design current and
>>maybe 2x and 1/2 as much.  Look for where the real part goes negative,
>>and consider whether that's going to find fertile ground for
>>oscillation.
> 
> The transfer curve of the fet is very nonlinear, and it's acting like a
> variable resistor, so the output time constant is continuously changing.
> I wouldn't want to try to write closed-form equations for the load-step
> response, or to evaluate stability over the load range. This is clearly
> a case where Spice wins.
> 
> The loop is unnecessarily hot, but was a first guess. It needs tweaking.
> What's important is to design a circuit that can be tweaked.
> 
> The LDO is powering a 4 gbit DDR3 ram and the FPGA bank that interfaces
> it. I have no good estimate of either the active or the idle current, or
> the time profile of the load current. The big output cap helps a lot
> here. I may need a dump resistor (R1) but probably not; gotta research
> the FPGA and the dram to be sure. The output can't go up much, given
> there's only 1.8 volts available.
> 
> 
> 
> 
>>(If you've got power gain and more than 180 degrees of phase shift,
>>you're pretty much guaranteed that the output impedance will go negative
>>at some frequency.)
> 
> Simulated load steps are a great way to estimate, well, load step
> response. Ringing suggests low phase margins.
> 
> 
>>To sweep for an impedance shove a voltage or current source in there
>>someplace (or use an existing one).  Set the DC value to zero (or use
>>what you had been for your simulation), set the AC value to 1, run the
>>sweep, and plot the current or voltage vs. frequency.  The admittance
>>(or impedance) jumps right out at you.
> 
> Load steps do that, in the time domain. But they account for the large
> nonlinearities, which AC analysis doesn't.

You've reminded me again of what I would have made my main line of 
research, had I been able to get it piled higher and deeper.

Basically, the world needs an extension of Lyapunov's 2nd method for 
determining stability that doesn't require a bunch of messing around 
solving nasty nonlinear differential equations, but that does cough up 
answers that are as intuitive as a resonant circuit's Q, or a phase 
margin on a Bode plot.

Dunno if you remember it, but Lyapunov's 2nd method is a way of 
determining if a nonlinear system is stable, and, to some extent, how 
fast it'll settle.  It involves cooking up a cost function that's 
analogous to the total system energy, then proving that the system always 
moves to a lower cost state.  I see no reason that it can't be done 
numerically, allowing one to basically say "is this system globally 
stable" and having something like LT Spice say "yes" or "no".  Having it 
cough up something analogous to a measure of Q in a resonant circuit 
would be a plus, so you know if it's on the verge of breaking into song.

-- 
www.wescottdesign.com

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#431048

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-12 16:11 -0700
Message-ID	<c4gtvbdqiloepnf0cemrqcfpomlv9smkak@4ax.com>
In reply to	#431032

On Wed, 12 Oct 2016 15:11:35 -0500, Tim Wescott
<tim@seemywebsite.really> wrote:

>On Wed, 12 Oct 2016 09:57:17 -0700, John Larkin wrote:
>
>> On Wed, 12 Oct 2016 11:21:49 -0500, Tim Wescott
>> <tim@seemywebsite.really> wrote:
>> 
>>>On Tue, 11 Oct 2016 22:09:59 -0700, John Larkin wrote:
>>>
>>>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>>>> easier to just do it from available parts than find a new regulator to
>>>> buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>>>> volts drain-source, the mosfet is acting like a variable resistor.
>>>> 
>>>Don't have time to put this on LT Spice, but do an AC analysis of the
>>>input and output impedances when it's running at design current and
>>>maybe 2x and 1/2 as much.  Look for where the real part goes negative,
>>>and consider whether that's going to find fertile ground for
>>>oscillation.
>> 
>> The transfer curve of the fet is very nonlinear, and it's acting like a
>> variable resistor, so the output time constant is continuously changing.
>> I wouldn't want to try to write closed-form equations for the load-step
>> response, or to evaluate stability over the load range. This is clearly
>> a case where Spice wins.
>> 
>> The loop is unnecessarily hot, but was a first guess. It needs tweaking.
>> What's important is to design a circuit that can be tweaked.
>> 
>> The LDO is powering a 4 gbit DDR3 ram and the FPGA bank that interfaces
>> it. I have no good estimate of either the active or the idle current, or
>> the time profile of the load current. The big output cap helps a lot
>> here. I may need a dump resistor (R1) but probably not; gotta research
>> the FPGA and the dram to be sure. The output can't go up much, given
>> there's only 1.8 volts available.
>> 
>> 
>> 
>> 
>>>(If you've got power gain and more than 180 degrees of phase shift,
>>>you're pretty much guaranteed that the output impedance will go negative
>>>at some frequency.)
>> 
>> Simulated load steps are a great way to estimate, well, load step
>> response. Ringing suggests low phase margins.
>> 
>> 
>>>To sweep for an impedance shove a voltage or current source in there
>>>someplace (or use an existing one).  Set the DC value to zero (or use
>>>what you had been for your simulation), set the AC value to 1, run the
>>>sweep, and plot the current or voltage vs. frequency.  The admittance
>>>(or impedance) jumps right out at you.
>> 
>> Load steps do that, in the time domain. But they account for the large
>> nonlinearities, which AC analysis doesn't.
>
>You've reminded me again of what I would have made my main line of 
>research, had I been able to get it piled higher and deeper.
>
>Basically, the world needs an extension of Lyapunov's 2nd method for 
>determining stability that doesn't require a bunch of messing around 
>solving nasty nonlinear differential equations, but that does cough up 
>answers that are as intuitive as a resonant circuit's Q, or a phase 
>margin on a Bode plot.
>
>Dunno if you remember it, but Lyapunov's 2nd method is a way of 
>determining if a nonlinear system is stable, and, to some extent, how 
>fast it'll settle.  It involves cooking up a cost function that's 
>analogous to the total system energy, then proving that the system always 
>moves to a lower cost state.  I see no reason that it can't be done 
>numerically, allowing one to basically say "is this system globally 
>stable" and having something like LT Spice say "yes" or "no".  Having it 
>cough up something analogous to a measure of Q in a resonant circuit 
>would be a plus, so you know if it's on the verge of breaking into song.

I also need to predict load step overshoot and undershoot, and pick
part values, so may as well Spice and fiddle until it looks good. "It
looks good" isn't a quantified error function.

It's shocking how much electronics I design versus how little serious
math I use. But I don't do long division with a quill pen on parchment
any more either. Seems to me that a good grounding in the theory
eventually transfers into fairly quantitative instincts, which becomes
the basis for simulation.

I know a guy who got a PhD in control theory, and it was really hairy.
Not bode plot stuff any more.

The mosfet might burst into RF oscillation too, but I'm guessing it's
unlikely with it acting like a resistor. But the gate resistor is good
insurance.


-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#431090

From	Winfield Hill <hill@rowland.harvard.edu>
Date	2016-10-13 04:52 -0700
Message-ID	<ntnsh902gs1@drn.newsguy.com>
In reply to	#431048

John Larkin wrote...
>
> The mosfet might burst into RF oscillation too, but I'm
> guessing it's unlikely with it acting like a resistor.
> But the gate resistor is good insurance.

 No, it's still a potential problem because of its
 high transconductance, lead inductances,** and the
 ceramic load cap.  Gate resistor may not help, but
 adding a little source resistance would help, say
 0.33 ohms for a 100mV drop at 300mA.  You have a
 resistor now after the cap, move the cap to the
 right, increase its value.   ** not in the sim.


-- 
 Thanks,
    - Win

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#431112

From	John Larkin <jjlarkin@highlandtechnology.com>
Date	2016-10-13 08:33 -0700
Message-ID	<50avvbh977jd9dq188f5m7n7pgevs53fus@4ax.com>
In reply to	#431090

On 13 Oct 2016 04:52:09 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>John Larkin wrote...
>>
>> The mosfet might burst into RF oscillation too, but I'm
>> guessing it's unlikely with it acting like a resistor.
>> But the gate resistor is good insurance.
>
> No, it's still a potential problem because of its
> high transconductance, lead inductances,** and the
> ceramic load cap.  Gate resistor may not help, but
> adding a little source resistance would help, say
> 0.33 ohms for a 100mV drop at 300mA.  You have a
> resistor now after the cap, move the cap to the
> right, increase its value.   ** not in the sim.

The 1mohm resistor is just there to plot the load current step; it's
not real. 

My experience is that adding source impedance makes a mosfet fet more
likely to RF oscillate, but adding a gate resistor always kills
oscillation.

I once theorized that the open-loop output impedance of an opamp would
act like a gate resistor and stop oscillation. That turned out to be
not so.

-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics

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#431159

From	Tim Wescott <seemywebsite@myfooter.really>
Date	2016-10-13 18:21 -0500
Message-ID	<xKKdnfhZVttBi53FnZ2dnUU7-IGdnZ2d@giganews.com>
In reply to	#431048

On Wed, 12 Oct 2016 16:11:39 -0700, John Larkin wrote:

> On Wed, 12 Oct 2016 15:11:35 -0500, Tim Wescott
> <tim@seemywebsite.really> wrote:
> 
>>On Wed, 12 Oct 2016 09:57:17 -0700, John Larkin wrote:
>>
>>> On Wed, 12 Oct 2016 11:21:49 -0500, Tim Wescott
>>> <tim@seemywebsite.really> wrote:
>>> 
>>>>On Tue, 11 Oct 2016 22:09:59 -0700, John Larkin wrote:
>>>>
>>>>> I need to make 1.5 volts (for DDR3 ram) from a 1.8 rail, and it was
>>>>> easier to just do it from available parts than find a new regulator
>>>>> to buy. Loop comp is the first wild guess, but it looks fine. At 0.3
>>>>> volts drain-source, the mosfet is acting like a variable resistor.
>>>>> 
>>>>Don't have time to put this on LT Spice, but do an AC analysis of the
>>>>input and output impedances when it's running at design current and
>>>>maybe 2x and 1/2 as much.  Look for where the real part goes negative,
>>>>and consider whether that's going to find fertile ground for
>>>>oscillation.
>>> 
>>> The transfer curve of the fet is very nonlinear, and it's acting like
>>> a variable resistor, so the output time constant is continuously
>>> changing.
>>> I wouldn't want to try to write closed-form equations for the
>>> load-step response, or to evaluate stability over the load range. This
>>> is clearly a case where Spice wins.
>>> 
>>> The loop is unnecessarily hot, but was a first guess. It needs
>>> tweaking.
>>> What's important is to design a circuit that can be tweaked.
>>> 
>>> The LDO is powering a 4 gbit DDR3 ram and the FPGA bank that
>>> interfaces it. I have no good estimate of either the active or the
>>> idle current, or the time profile of the load current. The big output
>>> cap helps a lot here. I may need a dump resistor (R1) but probably
>>> not; gotta research the FPGA and the dram to be sure. The output can't
>>> go up much, given there's only 1.8 volts available.
>>> 
>>> 
>>> 
>>> 
>>>>(If you've got power gain and more than 180 degrees of phase shift,
>>>>you're pretty much guaranteed that the output impedance will go
>>>>negative at some frequency.)
>>> 
>>> Simulated load steps are a great way to estimate, well, load step
>>> response. Ringing suggests low phase margins.
>>> 
>>> 
>>>>To sweep for an impedance shove a voltage or current source in there
>>>>someplace (or use an existing one).  Set the DC value to zero (or use
>>>>what you had been for your simulation), set the AC value to 1, run the
>>>>sweep, and plot the current or voltage vs. frequency.  The admittance
>>>>(or impedance) jumps right out at you.
>>> 
>>> Load steps do that, in the time domain. But they account for the large
>>> nonlinearities, which AC analysis doesn't.
>>
>>You've reminded me again of what I would have made my main line of
>>research, had I been able to get it piled higher and deeper.
>>
>>Basically, the world needs an extension of Lyapunov's 2nd method for
>>determining stability that doesn't require a bunch of messing around
>>solving nasty nonlinear differential equations, but that does cough up
>>answers that are as intuitive as a resonant circuit's Q, or a phase
>>margin on a Bode plot.
>>
>>Dunno if you remember it, but Lyapunov's 2nd method is a way of
>>determining if a nonlinear system is stable, and, to some extent, how
>>fast it'll settle.  It involves cooking up a cost function that's
>>analogous to the total system energy, then proving that the system
>>always moves to a lower cost state.  I see no reason that it can't be
>>done numerically, allowing one to basically say "is this system globally
>>stable" and having something like LT Spice say "yes" or "no".  Having it
>>cough up something analogous to a measure of Q in a resonant circuit
>>would be a plus, so you know if it's on the verge of breaking into song.
> 
> I also need to predict load step overshoot and undershoot, and pick part
> values, so may as well Spice and fiddle until it looks good. "It looks
> good" isn't a quantified error function.
> 
> It's shocking how much electronics I design versus how little serious
> math I use. But I don't do long division with a quill pen on parchment
> any more either. Seems to me that a good grounding in the theory
> eventually transfers into fairly quantitative instincts, which becomes
> the basis for simulation.
> 
> I know a guy who got a PhD in control theory, and it was really hairy.
> Not bode plot stuff any more.

Yup.  The Bode plot stuff is just what practitioners use to actually get 
stuff done (snarkity snark).

I feel that control theory has moved away from what ordinary people can 
grasp intuitively -- this is a shame.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

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LDO

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#431096

#431110

#430966

#430977

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#431068

#431003

#431009

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#431158

#431178

#431215

#431010

#431015

#431032

#431048

#431090

#431112

#431159