Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > sci.electronics.design > #454123 > unrolled thread

OpAmp design - from theory to practice

Back to article view | Back to sci.electronics.design

Contents

  OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-29 07:55 -0700
    Re: OpAmp design - from theory to practice Tim Wescott <tim@seemywebsite.com> - 2017-03-29 11:51 -0500
    Re: OpAmp design - from theory to practice Tim Wescott <tim@seemywebsite.com> - 2017-03-29 11:53 -0500
      Re: OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-30 01:02 -0700
        Re: OpAmp design - from theory to practice Martin Brown <'''newspam'''@nezumi.demon.co.uk> - 2017-03-30 10:54 +0100
          Re: OpAmp design - from theory to practice sroberts6328@gmail.com - 2017-03-30 05:25 -0700
        Re: OpAmp design - from theory to practice Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-03-30 14:37 +0200
          Re: OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-30 07:16 -0700
            Re: OpAmp design - from theory to practice Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-03-30 20:25 +0200
              Re: OpAmp design - from theory to practice bitrex <bitrex@de.lete.earthlink.net> - 2017-03-30 14:51 -0400
              Re: OpAmp design - from theory to practice Joerg <news@analogconsultants.com> - 2017-03-30 12:58 -0700
                Re: OpAmp design - from theory to practice pcdhobbs@gmail.com - 2017-03-30 13:25 -0700
                Re: OpAmp design - from theory to practice Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2017-03-30 23:55 +0200
                  Re: OpAmp design - from theory to practice Joerg <news@analogconsultants.com> - 2017-03-30 16:43 -0700
            Re: OpAmp design - from theory to practice George Herold <gherold@teachspin.com> - 2017-03-30 11:43 -0700
              Re: OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-30 15:02 -0700
              Re: OpAmp design - from theory to practice Jeroen Belleman <jeroen@nospam.please> - 2017-03-31 10:20 +0200
        Re: OpAmp design - from theory to practice Tim Wescott <tim@seemywebsite.com> - 2017-03-30 12:14 -0500
          Re: OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-30 15:05 -0700
    Re: OpAmp design - from theory to practice Joerg <news@analogconsultants.com> - 2017-03-30 10:45 -0700
      Re: OpAmp design - from theory to practice JM <dontreplytothis173@gmail.com> - 2017-03-30 19:32 +0100
        Re: OpAmp design - from theory to practice Joerg <news@analogconsultants.com> - 2017-03-30 12:47 -0700
          Re: OpAmp design - from theory to practice Francesco Zappon <cescozep@gmail.com> - 2017-03-30 15:16 -0700
            Re: OpAmp design - from theory to practice George Herold <gherold@teachspin.com> - 2017-03-30 16:11 -0700
            Re: OpAmp design - from theory to practice Joerg <news@analogconsultants.com> - 2017-03-30 16:57 -0700

Page 1 of 2  [1] 2  Next page →

#454123 — OpAmp design - from theory to practice

Hello everyone,

first post here. I hope I do not break any rule; let me know if this is the case.

Disclaimer: not native English speaker, forgive any mistake.

My background: master degree in physics (with a few courses in electronics). PhD in electronics/physics, doing 99% of digital design. My last encounter with analog design: 10 years ago (ie: my knowledge is a bit "rusty").

The problem: I work in high energy physics. Currently, my new project is to design a new version (in a new technology: from 250nm to 130nm) of a chip which has to perform current-to-frequency (CFC from now on) conversion. (for background information, if interested, you can read the previous designer work here: http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).

Basically, I need to design a CFC with input currents ranging from 1nA to 1mA, with a 40 us integration window and low input leakage (target: 100fA). Other details can be provided if needed.

The main problem is the design of the amplifier. I am studying the common designs and the usual architectures; BUT I have a difficult time in connecting the high-level specification of the device (CFC, min/max input current, etc..) with the low level specs of the amplifier (a fully differential OTA, if we keep the previous architecture) such as GBP, phase margin, slew rate, etc...

I understand that there is no such thing as a "magical" formula to design such circuits, but I assume that there must be, somewhere, a point from where to start, which is what I am missing here.

All the examples and designs I see (in tutorials or articles) start from the wanted specifications of the OpAmp, which would be good, if I had an idea on how to obtain them!

I hope that the question make sense to you.

Any help you can give is greatly appreciated!

thanks

Francesco

[toc] | [next] | [standalone]

#454126

On Wed, 29 Mar 2017 07:55:15 -0700, Francesco Zappon wrote:

> Hello everyone,
> 
> first post here. I hope I do not break any rule; let me know if this is
> the case.
> 
> Disclaimer: not native English speaker, forgive any mistake.
> 
> My background: master degree in physics (with a few courses in
> electronics). PhD in electronics/physics, doing 99% of digital design.
> My last encounter with analog design: 10 years ago (ie: my knowledge is
> a bit "rusty").
> 
> The problem: I work in high energy physics. Currently, my new project is
> to design a new version (in a new technology: from 250nm to 130nm) of a
> chip which has to perform current-to-frequency (CFC from now on)
> conversion. (for background information, if interested, you can read the
> previous designer work here:
> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).
> 
> Basically, I need to design a CFC with input currents ranging from 1nA
> to 1mA, with a 40 us integration window and low input leakage (target:
> 100fA). Other details can be provided if needed.
> 
> The main problem is the design of the amplifier. I am studying the
> common designs and the usual architectures; BUT I have a difficult time
> in connecting the high-level specification of the device (CFC, min/max
> input current, etc..) with the low level specs of the amplifier (a fully
> differential OTA, if we keep the previous architecture) such as GBP,
> phase margin, slew rate, etc...
> 
> I understand that there is no such thing as a "magical" formula to
> design such circuits, but I assume that there must be, somewhere, a
> point from where to start, which is what I am missing here.
> 
> All the examples and designs I see (in tutorials or articles) start from
> the wanted specifications of the OpAmp, which would be good, if I had an
> idea on how to obtain them!
> 
> I hope that the question make sense to you.
> 
> Any help you can give is greatly appreciated!

Here's the really short, over-simplified version that glosses over what 
could be a year-long senior/graduate-level class at a university:

For GBP and phase margin, model the op-amp as a perfect differential 
amplifier followed by a transfer function, i.e.

Vout = (V+ - V-) * (2 * %pi * GBW / s)

You may need to make your transfer function more complicated than this if 
the DC gain or the exact phase margin is important, but I hope you see 
where I'm going.

For things like input bias current and input bias voltage (if that's even 
important on an OTA), model the thing as an "ideal" part with voltages or 
currents injected into the relevant portions of the circuit.

For things like slew rates and other nonlinearities, either simulate and 
check that the nonlinearities aren't excited (i.e., the slew rates are 
never exceeded), or that the nonlinearities don't have much effect (which 
is pretty much what you have to do with crossover distortion).

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

[toc] | [prev] | [next] | [standalone]

#454127

On Wed, 29 Mar 2017 07:55:15 -0700, Francesco Zappon wrote:

> Hello everyone,
> 
> first post here. I hope I do not break any rule; let me know if this is
> the case.
> 
> Disclaimer: not native English speaker, forgive any mistake.
> 
> My background: master degree in physics (with a few courses in
> electronics). PhD in electronics/physics, doing 99% of digital design.
> My last encounter with analog design: 10 years ago (ie: my knowledge is
> a bit "rusty").
> 
> The problem: I work in high energy physics. Currently, my new project is
> to design a new version (in a new technology: from 250nm to 130nm) of a
> chip which has to perform current-to-frequency (CFC from now on)
> conversion. (for background information, if interested, you can read the
> previous designer work here:
> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).
> 
> Basically, I need to design a CFC with input currents ranging from 1nA
> to 1mA, with a 40 us integration window and low input leakage (target:
> 100fA). Other details can be provided if needed.
> 
> The main problem is the design of the amplifier. I am studying the
> common designs and the usual architectures; BUT I have a difficult time
> in connecting the high-level specification of the device (CFC, min/max
> input current, etc..) with the low level specs of the amplifier (a fully
> differential OTA, if we keep the previous architecture) such as GBP,
> phase margin, slew rate, etc...
> 
> I understand that there is no such thing as a "magical" formula to
> design such circuits, but I assume that there must be, somewhere, a
> point from where to start, which is what I am missing here.
> 
> All the examples and designs I see (in tutorials or articles) start from
> the wanted specifications of the OpAmp, which would be good, if I had an
> idea on how to obtain them!
> 
> I hope that the question make sense to you.
> 
> Any help you can give is greatly appreciated!

Just to _really_ throw a wrench into the works: <whatever>-to-frequency 
is an old idea that's mostly gone out of favor because of advances in 
digital processing and in ADC converters.  If I were on your team I would 
be questioning the system-level decision to continue using it -- but I'd 
be ready to back off from that if there's good reasons to stick with it.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

[toc] | [prev] | [next] | [standalone]

#454214

On Wednesday, 29 March 2017 18:53:21 UTC+2, Tim Wescott  wrote:

Hi Tim,

thanks a lot for the answer, first of all!


> Just to _really_ throw a wrench into the works: <whatever>-to-frequency 
> is an old idea that's mostly gone out of favor because of advances in 
> digital processing and in ADC converters.  If I were on your team I would 
> be questioning the system-level decision to continue using it -- but I'd 
> be ready to back off from that if there's good reasons to stick with it.

As I said, not an expert; I am not really sure what is the message you are trying to convey here, so I can give you some more details:

- we are designing a custom ASIC because discrete components cannot withstand the expected level of radiation (target is 10kgy in 20 years and probably more)
- given that, we cannot use FPGAs either! the ASIC must operate "standalone" and using basic components only (all validated for radiation hardness, of course)
- starting from this, I don't really see other solutions. I mean, maybe a self-switching, multi-range CFC might not be the best option (Sigma-Delta? pipeline?) but we have an input current and we need to digitize it, there is no escape from that :)

Thanks also for the other answer, of course.

Since you are not the first person giving me that answer, I am starting to wonder if my question is simply a non-question, because I am still left with my doubts.

Oh well, I'll keep studying I guess :)

thanks again!

Francesco

[toc] | [prev] | [next] | [standalone]

#454217

On 30/03/2017 09:02, Francesco Zappon wrote:
> On Wednesday, 29 March 2017 18:53:21 UTC+2, Tim Wescott  wrote:
>
>> Just to _really_ throw a wrench into the works:
>> <whatever>-to-frequency is an old idea that's mostly gone out of
>> favor because of advances in digital processing and in ADC
>> converters.  If I were on your team I would be questioning the
>> system-level decision to continue using it -- but I'd be ready to
>> back off from that if there's good reasons to stick with it.

We used to do it that way to bodge an analogue only high range onto what 
was originally designed as an ion counting system using the existing 
backend which was similar to an HEP multichannel analyser. It didn't do 
the detector much good lifetime wise but it sold more kit.

> As I said, not an expert; I am not really sure what is the message
> you are trying to convey here, so I can give you some more details:
>
> - we are designing a custom ASIC because discrete components cannot
> withstand the expected level of radiation (target is 10kgy in 20
> years and probably more) - given that, we cannot use FPGAs either!
> the ASIC must operate "standalone" and using basic components only
> (all validated for radiation hardness, of course) - starting from
> this, I don't really see other solutions. I mean, maybe a
> self-switching, multi-range CFC might not be the best option
> (Sigma-Delta? pipeline?) but we have an input current and we need to
> digitize it, there is no escape from that :)
>
> Thanks also for the other answer, of course.

Can the device not be shielded with lead foil to some extent?

This although now very dated might give you some inspiration as a 
starting point for a suitable current to frequency design:

http://www.spelektroniikka.fi/kuvat/lm331b.pdf

> Since you are not the first person giving me that answer, I am
> starting to wonder if my question is simply a non-question, because I
> am still left with my doubts.
>
> Oh well, I'll keep studying I guess :)

Mass spectrometers Faraday cups often do a high gain stabilised current 
to voltage conversion and then digitise the resulting voltage. This 
leaves you with thermal drift, gain stability and zero level problems.

-- 
Regards,
Martin Brown

[toc] | [prev] | [next] | [standalone]

#454220

CT scanners for medical x_ray use the current to frequency method at a similar current range. Off the shelf parts are available and many papers have been published, so that might be a place to start.

S.

[toc] | [prev] | [next] | [standalone]

#454221

Am 30.03.2017 um 10:02 schrieb Francesco Zappon:
> On Wednesday, 29 March 2017 18:53:21 UTC+2, Tim Wescott  wrote:

>> Just to _really_ throw a wrench into the works: <whatever>-to-frequency
>> is an old idea that's mostly gone out of favor because of advances in
>> digital processing and in ADC converters.  If I were on your team I would
>> be questioning the system-level decision to continue using it -- but I'd
>> be ready to back off from that if there's good reasons to stick with it.
>
> As I said, not an expert; I am not really sure what is the message you are
 > trying to convey here, so I can give you some more details:
>
> - we are designing a custom ASIC because discrete components cannot
 > withstand the expected level of radiation (target is 10kgy in 20 years
 > and probably more)
> - given that, we cannot use FPGAs either! the ASIC must operate "standalone"
 > and using basic components only (all validated for radiation 
hardness, of course)
> - starting from this, I don't really see other solutions. I mean, maybe a
 > self-switching, multi-range CFC might not be the best option
> (Sigma-Delta? pipeline?)  but we have an input current and we need to digitize it,
> there is no escape from that :)

I do not see the direct connection between cf converters and FPGAs,
but FPGAs can be used in a radiation infested environment. I just have
designed a few. You'll need to make registers, counters, RAMs triple
module redundant, but you need that in your custom chip also. The
contents of a RAM cell or flipflop that is hit is lost, even hard
wired gates can malfunction for some time.

Even voltage regulators that are hit can go berserk for a few
milliseconds. Be sure to have enough output capacitance so the
regulator cannot kill everything while it is delirious.

I have made a nice library that looks like std_logic / std_logic_vector
and that hides most of the nasty triple module redundancy details.
No, it is not available.

In RAM-based FPGAs like our prehistoric Virtexes is the additional
complication that the configuration is stored in RAM and that is
vulnerable. So, the config ram must be reloaded on a regular base
from the external ROM while the chip is running. That can be done
but it is a nasty thing to do, especially if the scrubber logic
is on the chip to be scrubbed.

You also cannot use distributed RAMs in the Xilinx case since that
are really small parts of the configuration ram made accessible to the
user. Our software lady found out that her Picoblaze registers would
auto-clear all few minutes. Turned out that it uses a distributed RAM
for its registers and that was overwritten by the scrubber. But it
proved at least that the scrubber works.

I could heal that by patching the Picoblaze to use solid flip flops
instead of the 16 bit RAMs. :-)

regards, Gerhard

[toc] | [prev] | [next] | [standalone]

#454229

On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann  wrote:
> Am 30.03.2017 um 10:02 schrieb Francesco Zappon:

[cut]

> regards, Gerhard

Hi Gerhard,

thanks for the answer.

I will give a general answer valid also for the others that commented on radiation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question).

People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time.

The comment on the FPGA was just meant to say that I cannot mount in the proximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)

thanks

Francesco

[toc] | [prev] | [next] | [standalone]

#454252

Am 30.03.2017 um 16:16 schrieb Francesco Zappon:
> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann  wrote:

> I will give a general answer valid also for the others that commented on radiation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question).
>
> People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time.
>
> The comment on the FPGA was just meant to say that I cannot mount in the proximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)

I assume then that you are abt. 2 or 3 hours by car from me in the
south/western direction.

Yes, if the FPGA gets warm from the radiation, that won't work. :-)
But good enough for space probes or devices on the ISS. After all,
there live some people. SEUs happen there, and it's bad if you lose
the counter that has yourtime/position in orbit.
	
But it surprised me that even robust things like voltage
regulators are affected.

cheers, Gerhard

[toc] | [prev] | [next] | [standalone]

#454256

On 03/30/2017 02:25 PM, Gerhard Hoffmann wrote:

> But it surprised me that even robust things like voltage
> regulators are affected.
>
> cheers, Gerhard

The old triode pass tube -> error amplifier tube with neon lamp in the 
cathode makes a great rad-hard voltage regulator! Pummel it with gamma 
all day long, it don't care. Neon lamps are especially resilient.

Little power-hungry, though.

[toc] | [prev] | [next] | [standalone]

#454265

On 2017-03-30 11:25, Gerhard Hoffmann wrote:
> Am 30.03.2017 um 16:16 schrieb Francesco Zappon:
>> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann  wrote:
>
>> I will give a general answer valid also for the others that commented
>> on radiation hardness: we are operating with a 7 TeV beam of protons
>> (you might guess where I am working, at this point :D) and the
>> radiation areas are *very* harsh. This is not a problem that can be
>> solved just by shielding or some smart tricks (but we are diverging
>> from my question).
>>
>> People way smarter than me tell me that no FPGA can withstand that
>> kind of radiation for a reasonably long amount of time.
>>
>> The comment on the FPGA was just meant to say that I cannot mount in
>> the proximity of the chip I am designing an FPGA to control it.
>> Nothing more than that; you are right when you say that a CFC and an
>> FPGA have nothing to do with each other :)
>
> I assume then that you are abt. 2 or 3 hours by car from me in the
> south/western direction.
>
> Yes, if the FPGA gets warm from the radiation, that won't work. :-)
> But good enough for space probes or devices on the ISS. After all,
> there live some people. SEUs happen there, and it's bad if you lose
> the counter that has yourtime/position in orbit.
>
> But it surprised me that even robust things like voltage
> regulators are affected.
>

Even space-rated ones?

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slyt532d

http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548

http://www.linear.com/parametric/Space_Qualified_Linear_Regulators
http://www.linear.com/parametric/Space_Qualified_Switching_Regulators

I found the old uA723 to be of cast-iron behavior in nasty environments 
but I don't know about its formal radiation tolerance.

-- 
Regards, Joerg

http://www.analogconsultants.com/

[toc] | [prev] | [next] | [standalone]

#454268

  
I'm not an IC designer, but I used to pal around with some. First you need to do the chip on a SOI process and not bulk. Second, use processes with wider features by preference. 

I-to-F is actually reasonably nice, since it uses time and frequency and is immune to voltage offsets. Much better than V-F. 

Cheers

Phil Hobbs

[toc] | [prev] | [next] | [standalone]

#454281

Am 30.03.2017 um 21:58 schrieb Joerg:
> On 2017-03-30 11:25, Gerhard Hoffmann wrote:

>> But it surprised me that even robust things like voltage
>> regulators are affected.
>>
>
> Even space-rated ones?

> ...
> http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548
> ...

The documentation of the ST RHFL4913 & friends mentions exactly this,
including the workaround with the large output capacitors.

cheers, Gerhard

[toc] | [prev] | [next] | [standalone]

#454297

On 2017-03-30 14:55, Gerhard Hoffmann wrote:
> Am 30.03.2017 um 21:58 schrieb Joerg:
>> On 2017-03-30 11:25, Gerhard Hoffmann wrote:
>
>>> But it surprised me that even robust things like voltage
>>> regulators are affected.
>>>
>>
>> Even space-rated ones?
>
>> ...
>> http://www.st.com/content/st_com/en/products/aerospace-and-defense-products/space-products/rad-hard-pwm-controllers.html?querycriteria=productId=SC1548
>>
>> ...
>
> The documentation of the ST RHFL4913 & friends mentions exactly this,
> including the workaround with the large output capacitors.
>

Can't find the P/N RHFL4913 but yes, of course you need sufficient 
output caps in such an application.

Then with many LDOs there is often inadequate stability and those I 
would never use in hi-rel.

-- 
Regards, Joerg

http://www.analogconsultants.com/

[toc] | [prev] | [next] | [standalone]

#454255

On Thursday, March 30, 2017 at 10:16:47 AM UTC-4, Francesco Zappon wrote:
> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann  wrote:
> > Am 30.03.2017 um 10:02 schrieb Francesco Zappon:
> 
> [cut]
> 
> > regards, Gerhard
> 
> Hi Gerhard,
> 
> thanks for the answer.
> 
> I will give a general answer valid also for the others that commented on radiation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question).
> 
> People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time.
> 
> The comment on the FPGA was just meant to say that I cannot mount in the proximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)
> 
> thanks
> 
> Francesco

If you are at Cern, I would think there are many people there who know more about 
your problem, than we do here... where's Jeroen Belleman?

George H. 

[toc] | [prev] | [next] | [standalone]

#454285

On Thursday, 30 March 2017 20:43:34 UTC+2, George Herold  wrote:

> 
> If you are at Cern, I would think there are many people there who know more 
> about your problem, than we do here... where's Jeroen Belleman?

You are right. Many experts around. Sadly, everyone is busy and I am not in direct contact with them on a daily basis, so it is difficult to get some collaboration going. But we are working on it :)

Francesco

[toc] | [prev] | [next] | [standalone]

#454368

On 2017-03-30 20:43, George Herold wrote:
> On Thursday, March 30, 2017 at 10:16:47 AM UTC-4, Francesco Zappon
> wrote:
>> On Thursday, 30 March 2017 14:37:21 UTC+2, Gerhard Hoffmann
>> wrote:
>>> Am 30.03.2017 um 10:02 schrieb Francesco Zappon:
>>
>> [cut]
>>
>>> regards, Gerhard
>>
>> Hi Gerhard,
>>
>> thanks for the answer.
>>
>> I will give a general answer valid also for the others that
>> commented on radiation hardness: we are operating with a 7 TeV beam
>> of protons (you might guess where I am working, at this point :D)
>> and the radiation areas are *very* harsh. This is not a problem
>> that can be solved just by shielding or some smart tricks (but we
>> are diverging from my question).
>>
>> People way smarter than me tell me that no FPGA can withstand that
>> kind of radiation for a reasonably long amount of time.
>>
>> The comment on the FPGA was just meant to say that I cannot mount
>> in the proximity of the chip I am designing an FPGA to control it.
>> Nothing more than that; you are right when you say that a CFC and
>> an FPGA have nothing to do with each other :)
>>
>> thanks
>>
>> Francesco
>
> If you are at Cern, I would think there are many people there who
> know more about your problem, than we do here... where's Jeroen
> Belleman?
>
> George H.
>

I'm right here. Francesco and I are even in the same beam
instrumentation group (although I've never met him, I think).
I have my own little problems at the moment. We're about to
start up the accelerators and I have lots of work that can't
wait.

Jeroen Belleman

[toc] | [prev] | [next] | [standalone]

#454246

On Thu, 30 Mar 2017 01:02:23 -0700, Francesco Zappon wrote:

> On Wednesday, 29 March 2017 18:53:21 UTC+2, Tim Wescott  wrote:
> 
> Hi Tim,
> 
> thanks a lot for the answer, first of all!
> 
> 
>> Just to _really_ throw a wrench into the works: <whatever>-to-frequency
>> is an old idea that's mostly gone out of favor because of advances in
>> digital processing and in ADC converters.  If I were on your team I
>> would be questioning the system-level decision to continue using it --
>> but I'd be ready to back off from that if there's good reasons to stick
>> with it.
> 
> As I said, not an expert; I am not really sure what is the message you
> are trying to convey here, so I can give you some more details:

It was really simple: you said you aren't an expert, that you're 
revamping an old design, and then you proposed a method that has been 
superseded by current-to-voltage followed by ADC in many places.  That 
made me think that maybe there's a better approach.

This doesn't mean that I'm convinced that you should change approaches -- 
perhaps current to frequency is best, or at least changing from that to 
some other method would require to many changes elsewhere in the system 
for it to be viable.

> - we are designing a custom ASIC because discrete components cannot
> withstand the expected level of radiation (target is 10kgy in 20 years
> and probably more)

'K.  So that affects whether or not a local ADC is a reasonable thing to 
consider.

> - given that, we cannot use FPGAs either! the ASIC must operate
> "standalone" and using basic components only (all validated for
> radiation hardness, of course)

I never suggested an FPGA.

> - starting from this, I don't really see other solutions. I mean, maybe
> a self-switching, multi-range CFC might not be the best option
> (Sigma-Delta? pipeline?) but we have an input current and we need to
> digitize it, there is no escape from that :)

If you have the bandwidth for the data, using a sigma-delta modulator on 
the front end may work better -- just output raw or only lightly 
processed bits from the 1-bit ADC, and do the actual processing somewhere 
at a lower radiation level.

> Thanks also for the other answer, of course.
> 
> Since you are not the first person giving me that answer, I am starting
> to wonder if my question is simply a non-question, because I am still
> left with my doubts.

I'm thinking like a system-level engineer, and part of that job entails 
re-thinking previous assumptions.  I'm always confused at this stage of a 
project, or at least find myself faced with more choices than I'd prefer.

Basically, at this stage, you do some feasibility studies of each 
approach, and ask yourself which ones are better.  Since you're doing an 
upgrade of an existing system, you want to give a lot of weight to what's 
already there.

And it sounds like you're a junior member of the team, so someone else 
may have already thought of all of this and either determined from first 
principles that the current approach is best, or they're married to it 
and won't budge even if it's the worst.  So at your level you may not get 
to make the decision to change at all (but if you think some other 
approach might be better you should prepare your mind to not be dismayed 
by any answer, and then ask).

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

[toc] | [prev] | [next] | [standalone]

#454288

On Thursday, 30 March 2017 19:14:47 UTC+2, Tim Wescott  wrote:

Hi Tim,

> 
> If you have the bandwidth for the data, using a sigma-delta modulator on 
> the front end may work better -- just output raw or only lightly 
> processed bits from the 1-bit ADC, and do the actual processing somewhere 
> at a lower radiation level.

[cut]

> 
> I'm thinking like a system-level engineer, and part of that job entails 
> re-thinking previous assumptions.  I'm always confused at this stage of a 
> project, or at least find myself faced with more choices than I'd prefer.
> 
> Basically, at this stage, you do some feasibility studies of each 
> approach, and ask yourself which ones are better.  Since you're doing an 
> upgrade of an existing system, you want to give a lot of weight to what's 
> already there.

thanks a lot for the tips!


> 
> And it sounds like you're a junior member of the team, so someone else 
> may have already thought of all of this and either determined from first 
> principles that the current approach is best, or they're married to it 
> and won't budge even if it's the worst.  So at your level you may not get 
> to make the decision to change at all (but if you think some other 
> approach might be better you should prepare your mind to not be dismayed 
> by any answer, and then ask).

The choice of whether changing approach or not is also due to time constraints. 

But anyway, thanks for any suggestion so far!

Francesco

[toc] | [prev] | [next] | [standalone]

#454250

On 2017-03-29 07:55, Francesco Zappon wrote:
> Hello everyone,
>
> first post here. I hope I do not break any rule; let me know if this
> is the case.
>

There are not many rules out here anymore :-)

<ducking for cover now>


> Disclaimer: not native English speaker, forgive any mistake.
>

Your English looks very good (I am non-native myself).


> My background: master degree in physics (with a few courses in
> electronics). PhD in electronics/physics, doing 99% of digital
> design. My last encounter with analog design: 10 years ago (ie: my
> knowledge is a bit "rusty").
>
> The problem: I work in high energy physics. Currently, my new project
> is to design a new version (in a new technology: from 250nm to 130nm)


130nm isn't considered very new these days but, of course, for radhard 
your selection will be limited. New designs are still done in the larger 
geometries. The most recent one I was involved in was 300nm.


> of a chip which has to perform current-to-frequency (CFC from now on)
> conversion. (for background information, if interested, you can read
> the previous designer work here:
> http://dx.doi.org/10.1016/j.mejo.2013.08.020 if you have access).
>

Do you have a link where this paper can be accessed without charge? From 
non-subscribers they want about $40 just to take a look.


> Basically, I need to design a CFC with input currents ranging from
> 1nA to 1mA, with a 40 us integration window and low input leakage
> (target: 100fA). Other details can be provided if needed.
>
> The main problem is the design of the amplifier. I am studying the
> common designs and the usual architectures; BUT I have a difficult
> time in connecting the high-level specification of the device (CFC,
> min/max input current, etc..) with the low level specs of the
> amplifier (a fully differential OTA, if we keep the previous
> architecture) such as GBP, phase margin, slew rate, etc...
>

1nA gets you into noise floor issues with the first stage if the 
integration window means >20kHz bandwidth.


> I understand that there is no such thing as a "magical" formula to
> design such circuits, but I assume that there must be, somewhere, a
> point from where to start, which is what I am missing here.
>
> All the examples and designs I see (in tutorials or articles) start
> from the wanted specifications of the OpAmp, which would be good, if
> I had an idea on how to obtain them!
>
> I hope that the question make sense to you.
>
> Any help you can give is greatly appreciated!
>

Usually the first stage needed would be a transimpedance amplifier or 
TIA, in other words a glorified current to voltage converter, followed 
by a V/F conversion or another more modern method. Phil Hobbs here in 
this group is the guru on low noise TIAs, maybe he could chime in.

It might also help to talk to these guys:

http://ams.aeroflex.com/pagesproduct/datasheets/MilAero_ASIC_Brochure.pdf

-- 
Regards, Joerg

http://www.analogconsultants.com/

[toc] | [prev] | [next] | [standalone]

Page 1 of 2  [1] 2  Next page →

Back to top | Article view | sci.electronics.design

csiph-web