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FET G-S voltage limits

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  FET G-S voltage limits Tim Wescott <seemywebsite@myfooter.really> - 2017-03-24 16:34 -0500
    Re: FET G-S voltage limits Joerg <news@analogconsultants.com> - 2017-03-24 14:41 -0700
      Re: FET G-S voltage limits Tim Wescott <seemywebsite@myfooter.really> - 2017-03-24 17:02 -0500
        Re: FET G-S voltage limits Joerg <news@analogconsultants.com> - 2017-03-24 15:42 -0700
    Re: FET G-S voltage limits dagmargoodboat@yahoo.com - 2017-03-24 14:42 -0700
    Re: FET G-S voltage limits John Larkin <jjlarkinxyxy@highlandtechnology.com> - 2017-03-24 15:33 -0700
      Re: FET G-S voltage limits Joerg <news@analogconsultants.com> - 2017-03-24 16:08 -0700
        Re: FET G-S voltage limits John Larkin <jjlarkinxyxy@highlandtechnology.com> - 2017-03-24 16:24 -0700
    Re: FET G-S voltage limits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-25 03:01 -0500
    Re: FET G-S voltage limits Robert Baer <robertbaer@localnet.com> - 2017-03-30 23:37 -0800

#453452 — FET G-S voltage limits

A customer of mine is repurposing a board that I designed for them 
several years ago, and we're running into some interesting issues.

One of the issues is that there's a master turn-on to the power section 
of the board that's operated by pulling the gate of a P-channel FET low.  
I just noticed that the thing is rated for a maximum G-S voltage of 20V 
-- we had been putting 24V on it (oops), and now we're putting about 29V 
on it (bigger oops).

We're now seeing that part get hot at high current draw, but we've 
identified two other possible mechanisms for that happening.  I'm trying 
to sort through the suspects to find a culprit.

How much does the maximum G-S voltage rating on a FET matter?  Could it 
make a FET overheat at high currents, or would it just cause the whole 
thing to pop somehow?

TIA

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

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#453453

On 2017-03-24 14:34, Tim Wescott wrote:
> A customer of mine is repurposing a board that I designed for them
> several years ago, and we're running into some interesting issues.
>
> One of the issues is that there's a master turn-on to the power section
> of the board that's operated by pulling the gate of a P-channel FET low.
> I just noticed that the thing is rated for a maximum G-S voltage of 20V
> -- we had been putting 24V on it (oops), and now we're putting about 29V
> on it (bigger oops).
>
> We're now seeing that part get hot at high current draw, but we've
> identified two other possible mechanisms for that happening.  I'm trying
> to sort through the suspects to find a culprit.
>
> How much does the maximum G-S voltage rating on a FET matter?  Could it
> make a FET overheat at high currents, or would it just cause the whole
> thing to pop somehow?
>

Many FETs can actually take in excess of 50V on the gate. Of course, 
that is not a legit design because abs max is usually 20V. There are a 
few FETs where Vgs is rated abs max at 30V.

The failure mechanism would be a sudden breakdown of the oxide layer and 
then you have a conductive path from whatever is driving the gate to the 
power path (the channel). A FET getting hot at such high drive level has 
other causes such as very high current and consequential ohmic losses, 
or too frequenct and sluggish switching which causes transistion losses.

If you still can, add a 12-15V zener from gate to source and a series 
resistor towards whatever drives the gate.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#453456

On Fri, 24 Mar 2017 14:41:24 -0700, Joerg wrote:

> On 2017-03-24 14:34, Tim Wescott wrote:
>> A customer of mine is repurposing a board that I designed for them
>> several years ago, and we're running into some interesting issues.
>>
>> One of the issues is that there's a master turn-on to the power section
>> of the board that's operated by pulling the gate of a P-channel FET
>> low.
>> I just noticed that the thing is rated for a maximum G-S voltage of 20V
>> -- we had been putting 24V on it (oops), and now we're putting about
>> 29V on it (bigger oops).
>>
>> We're now seeing that part get hot at high current draw, but we've
>> identified two other possible mechanisms for that happening.  I'm
>> trying to sort through the suspects to find a culprit.
>>
>> How much does the maximum G-S voltage rating on a FET matter?  Could it
>> make a FET overheat at high currents, or would it just cause the whole
>> thing to pop somehow?
>>
>>
> Many FETs can actually take in excess of 50V on the gate. Of course,
> that is not a legit design because abs max is usually 20V. There are a
> few FETs where Vgs is rated abs max at 30V.
> 
> The failure mechanism would be a sudden breakdown of the oxide layer and
> then you have a conductive path from whatever is driving the gate to the
> power path (the channel). A FET getting hot at such high drive level has
> other causes such as very high current and consequential ohmic losses,
> or too frequenct and sluggish switching which causes transistion losses.
> 
> If you still can, add a 12-15V zener from gate to source and a series
> resistor towards whatever drives the gate.

It went unnoticed until the thing went into production, and it's 
certainly not exhibiting the symptoms you cite.  It's not the prime 
candidate at any rate -- but I wanted to be sure.

Our prime candidate is that the part that's actually getting assembled 
onto the board isn't what's in the BOM at my customer's site, and there's 
about an 8x difference in RDS_ON.  It's not clear where the mixup 
occurred, but at the current levels where the problem is exhibiting 
itself the installed part will dissipate 16W, where the part that I 
designed in will dissipate less than two.  It's a D2PAK, but with thermal 
features that are more in line with 2W dissipation than 16.

The new use case has the thing working at high current for more extended 
periods of time.  The part is cooking the board underneath it, without 
(to date) burning up itself -- although I expect that it's going to live 
a severely shortened life.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

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#453463

On 2017-03-24 15:02, Tim Wescott wrote:
> On Fri, 24 Mar 2017 14:41:24 -0700, Joerg wrote:
>
>> On 2017-03-24 14:34, Tim Wescott wrote:
>>> A customer of mine is repurposing a board that I designed for them
>>> several years ago, and we're running into some interesting issues.
>>>
>>> One of the issues is that there's a master turn-on to the power section
>>> of the board that's operated by pulling the gate of a P-channel FET
>>> low.
>>> I just noticed that the thing is rated for a maximum G-S voltage of 20V
>>> -- we had been putting 24V on it (oops), and now we're putting about
>>> 29V on it (bigger oops).
>>>
>>> We're now seeing that part get hot at high current draw, but we've
>>> identified two other possible mechanisms for that happening.  I'm
>>> trying to sort through the suspects to find a culprit.
>>>
>>> How much does the maximum G-S voltage rating on a FET matter?  Could it
>>> make a FET overheat at high currents, or would it just cause the whole
>>> thing to pop somehow?
>>>
>>>
>> Many FETs can actually take in excess of 50V on the gate. Of course,
>> that is not a legit design because abs max is usually 20V. There are a
>> few FETs where Vgs is rated abs max at 30V.
>>
>> The failure mechanism would be a sudden breakdown of the oxide layer and
>> then you have a conductive path from whatever is driving the gate to the
>> power path (the channel). A FET getting hot at such high drive level has
>> other causes such as very high current and consequential ohmic losses,
>> or too frequenct and sluggish switching which causes transistion losses.
>>
>> If you still can, add a 12-15V zener from gate to source and a series
>> resistor towards whatever drives the gate.
>
> It went unnoticed until the thing went into production, and it's
> certainly not exhibiting the symptoms you cite.  It's not the prime
> candidate at any rate -- but I wanted to be sure.
>

It would be rare to have a gate blow through at 29V but the design is 
technically out of spec.


> Our prime candidate is that the part that's actually getting assembled
> onto the board isn't what's in the BOM at my customer's site, and there's
> about an 8x difference in RDS_ON.  It's not clear where the mixup
> occurred, but at the current levels where the problem is exhibiting
> itself the installed part will dissipate 16W, where the part that I
> designed in will dissipate less than two.  It's a D2PAK, but with thermal
> features that are more in line with 2W dissipation than 16.
>
> The new use case has the thing working at high current for more extended
> periods of time.  The part is cooking the board underneath it, without
> (to date) burning up itself -- although I expect that it's going to live
> a severely shortened life.
>

Yes, it'll roast the board and eventually destroy the FET. It is really 
hard to sink away this much power from a D2PAK. You'd need many 
square-inches of 4oz copper. Even with heat-conductive foam it is a problem.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#453454

On Friday, March 24, 2017 at 5:34:25 PM UTC-4, Tim Wescott wrote:
> A customer of mine is repurposing a board that I designed for them 
> several years ago, and we're running into some interesting issues.
> 
> One of the issues is that there's a master turn-on to the power section 
> of the board that's operated by pulling the gate of a P-channel FET low.  
> I just noticed that the thing is rated for a maximum G-S voltage of 20V 
> -- we had been putting 24V on it (oops), and now we're putting about 29V 
> on it (bigger oops).
> 
> We're now seeing that part get hot at high current draw, but we've 
> identified two other possible mechanisms for that happening.  I'm trying 
> to sort through the suspects to find a culprit.
> 
> How much does the maximum G-S voltage rating on a FET matter?  Could it 
> make a FET overheat at high currents, or would it just cause the whole 
> thing to pop somehow?
> 
> TIA

Excess Vgs on a MOSFET ruptures the gate oxide, which often shorts it
gate-to-source.

Cheers,
James Arthur

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#453462

On Fri, 24 Mar 2017 16:34:17 -0500, Tim Wescott
<seemywebsite@myfooter.really> wrote:

>A customer of mine is repurposing a board that I designed for them 
>several years ago, and we're running into some interesting issues.
>
>One of the issues is that there's a master turn-on to the power section 
>of the board that's operated by pulling the gate of a P-channel FET low.  
>I just noticed that the thing is rated for a maximum G-S voltage of 20V 
>-- we had been putting 24V on it (oops), and now we're putting about 29V 
>on it (bigger oops).
>
>We're now seeing that part get hot at high current draw, but we've 
>identified two other possible mechanisms for that happening.  I'm trying 
>to sort through the suspects to find a culprit.
>
>How much does the maximum G-S voltage rating on a FET matter?  Could it 
>make a FET overheat at high currents, or would it just cause the whole 
>thing to pop somehow?
>
>TIA

If the fet is ESD protected, it may have something like a 22 volt
zener from gate to source, with some resistance out to the gate pin.
Lots of gate drive will heat up that zener and resistor. You might
check for gate current, or kluge in a 10K series resistor.

I've tested fet gates to destruction, and something like 70 volts is
common. The specs tend to be very conservative on Vgs-max if it
doesn't have the ESD zener. Once a non-protected gate breaks down, the
fet is dead.

Vds breakdown voltages are sometimes pretty close, like 20% over data
sheet max. Controlled avalanche or something.

It's fun to destroy parts. But not at customer sites.





-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#453466

On 2017-03-24 15:33, John Larkin wrote:

[...]


> Vds breakdown voltages are sometimes pretty close, like 20% over data
> sheet max. Controlled avalanche or something.
>

Some people use them as zero-cost snubbers in flybacks. Crazy.


> It's fun to destroy parts. But not at customer sites.
>

https://www.youtube.com/watch?v=4GEGMXc_LKE

Though I am sure that was a transformer and not a transistor.

-- 
Regards, Joerg

http://www.analogconsultants.com/

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#453467

On Fri, 24 Mar 2017 16:08:55 -0700, Joerg <news@analogconsultants.com>
wrote:

>On 2017-03-24 15:33, John Larkin wrote:
>
>[...]
>
>
>> Vds breakdown voltages are sometimes pretty close, like 20% over data
>> sheet max. Controlled avalanche or something.
>>
>
>Some people use them as zero-cost snubbers in flybacks. Crazy.

For things like solenoid coils and fuel injectors and matrix printer
heads, the fets are designed to absorb the flyback.

>
>
>> It's fun to destroy parts. But not at customer sites.
>>
>
>https://www.youtube.com/watch?v=4GEGMXc_LKE
>
>Though I am sure that was a transformer and not a transistor.

Big bang. Probably a SOT-223.


-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#453534

My recent post with this link seems relevant:
https://hackaday.io/project/16384-enhancement-to-depletion

That's probably significant when very near actual gate breakdown, so 
needless you say, you shouldn't want to be anywhere near either condition.

No opportunity to hack in a resistor and zener?

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com


"Tim Wescott" <seemywebsite@myfooter.really> wrote in message 
news:6OWdnVi4pOhEDUjFnZ2dnUU7-QWdnZ2d@giganews.com...
>A customer of mine is repurposing a board that I designed for them
> several years ago, and we're running into some interesting issues.
>
> One of the issues is that there's a master turn-on to the power section
> of the board that's operated by pulling the gate of a P-channel FET low.
> I just noticed that the thing is rated for a maximum G-S voltage of 20V
> -- we had been putting 24V on it (oops), and now we're putting about 29V
> on it (bigger oops).
>
> We're now seeing that part get hot at high current draw, but we've
> identified two other possible mechanisms for that happening.  I'm trying
> to sort through the suspects to find a culprit.
>
> How much does the maximum G-S voltage rating on a FET matter?  Could it
> make a FET overheat at high currents, or would it just cause the whole
> thing to pop somehow?
>
> TIA
>
> -- 
>
> Tim Wescott
> Wescott Design Services
> http://www.wescottdesign.com
>
> I'm looking for work -- see my website! 

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#454359

Tim Wescott wrote:
> A customer of mine is repurposing a board that I designed for them
> several years ago, and we're running into some interesting issues.
>
> One of the issues is that there's a master turn-on to the power section
> of the board that's operated by pulling the gate of a P-channel FET low.
> I just noticed that the thing is rated for a maximum G-S voltage of 20V
> -- we had been putting 24V on it (oops), and now we're putting about 29V
> on it (bigger oops).
>
> We're now seeing that part get hot at high current draw, but we've
> identified two other possible mechanisms for that happening.  I'm trying
> to sort through the suspects to find a culprit.
>
> How much does the maximum G-S voltage rating on a FET matter?  Could it
> make a FET overheat at high currents, or would it just cause the whole
> thing to pop somehow?
>
> TIA
>
   My guess is that there are micro gate insulation breakdowns - like a 
pinhole; those will never be seen via a nominal leakage test.
   Perhaps ions are injected at those sites, causing localized 
mis-behavior..

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