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[PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii

Started byDavid Wu <david.wu@rock-chips.com>
First post2017-09-30 14:20 +0200
Last post2017-09-30 17:10 +0200
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  [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii David Wu <david.wu@rock-chips.com> - 2017-09-30 14:20 +0200
    Re: [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii Heiko Stuebner <heiko@sntech.de> - 2017-09-30 17:10 +0200

#1742625 — [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii

FromDavid Wu <david.wu@rock-chips.com>
Date2017-09-30 14:20 +0200
Subject[PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii
Message-ID<uvoUp-40Q-3@gated-at.bofh.it>
If the gmac-m1 optimization(bit10) is selected, the gpio function
of gmac pins is not valid. We may use the rmii mode for gmac interface,
the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not
used could be taken as gpio function. So gmac_rxd0m1 selects the bit2,
and gmac_rxd0m3 select bit10 is more correct.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c7c9beb..9e0cabf 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -900,12 +900,19 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 		.route_offset = 0x50,
 		.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
 	}, {
-		/* gmac-m1-optimized_rxd0 */
+		/* gmac-m1_rxd0 */
 		.bank_num = 1,
 		.pin = 11,
 		.func = 2,
 		.route_offset = 0x50,
-		.route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
+		.route_val = BIT(16 + 2) | BIT(2),
+	}, {
+		/* gmac-m1-optimized_rxd3 */
+		.bank_num = 1,
+		.pin = 14,
+		.func = 2,
+		.route_offset = 0x50,
+		.route_val = BIT(16 + 10) | BIT(10),
 	}, {
 		/* pdm_sdi0m0 */
 		.bank_num = 2,
-- 
1.9.1

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#1742636

FromHeiko Stuebner <heiko@sntech.de>
Date2017-09-30 17:10 +0200
Message-ID<uvryV-5MV-1@gated-at.bofh.it>
In reply to#1742625
Hi David,

Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu:
> If the gmac-m1 optimization(bit10) is selected, the gpio function
> of gmac pins is not valid. We may use the rmii mode for gmac interface,
> the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not
> used could be taken as gpio function. So gmac_rxd0m1 selects the bit2,
> and gmac_rxd0m3 select bit10 is more correct.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>

the patch subject should mention the the rk3328 whose routing gets fixed
(like adding a simple "on rk3328" to it), otherwise

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

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