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[RFC 0/4] Add Ingenic X1000 SoC Support

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  [RFC 0/4] Add Ingenic X1000 SoC Support PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> - 2017-09-27 17:20 +0200
    [RFC 1/4] dt-bindings: Add Ingenic X1000 SoC clock define PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> - 2017-09-27 17:20 +0200
    [RFC 4/4] MIPS: Ingenic: Add Halley2 development board support PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> - 2017-09-27 17:20 +0200
    [RFC 2/4] clk: Add Ingenic X1000 CGU driver PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> - 2017-09-27 17:20 +0200

#1740821 — [RFC 0/4] Add Ingenic X1000 SoC Support

Add support for Ingenic X1000 SoC. This patch set provides enough bits
to boot a kernel to an initramfs user space.

I implemented this code during 2016. Boot stuck at "calibrating delay
loop ...". Now I have fixed the issue by setting the correct irq. I do
not have access to this device anymore so could not test the fix.
Marking this patch series as RFC as this needs to be tested.

Test and feedback appreciated.

This series enables uart, timer and interrupt controller. As this is
very minimal a static elf binary should be used as init and should be
available in initramfs.

PrasannaKumar Muralidharan (4):
  dt-bindings: Add Ingenic X1000 SoC clock define
  clk: Add Ingenic X1000 CGU driver
  MIPS: Ingenic: Initial X1000 SoC support
  MIPS: Ingenic: Add Halley2 development board support

 arch/mips/boot/dts/ingenic/Makefile    |   1 +
 arch/mips/boot/dts/ingenic/halley2.dts |  46 ++++++++
 arch/mips/boot/dts/ingenic/x1000.dtsi  |  93 +++++++++++++++
 arch/mips/configs/halley2_defconfig    |  61 ++++++++++
 arch/mips/jz4740/Kconfig               |  10 ++
 arch/mips/jz4740/time.c                |   2 +-
 drivers/clk/ingenic/Makefile           |   1 +
 drivers/clk/ingenic/x1000-cgu.c        | 203 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/x1000-cgu.h  |  46 ++++++++
 9 files changed, 462 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
 create mode 100644 arch/mips/configs/halley2_defconfig
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h

-- 
2.10.0

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#1740823 — [RFC 1/4] dt-bindings: Add Ingenic X1000 SoC clock define

Ingenic X1000 SoC has different set of peripherals than JZ4780 and
JZ4740. Add a new device tree binding for the clock.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 include/dt-bindings/clock/x1000-cgu.h | 46 +++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h

diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 0000000..17f05bc
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+/* Add details for other peripherals when their support is added */
+#define X1000_CLK_EXCLK		0
+#define X1000_CLK_RTCLK		(X1000_CLK_EXCLK + 1)
+#define X1000_CLK_APLL		(X1000_CLK_RTCLK + 1)
+#define X1000_CLK_MPLL		(X1000_CLK_APLL + 1)
+
+#define X1000_CLK_SCLKA		(X1000_CLK_MPLL + 1)
+#define X1000_CLK_CPUMUX	(X1000_CLK_SCLKA + 1)
+#define X1000_CLK_CPU		(X1000_CLK_CPUMUX + 1)
+#define X1000_CLK_L2CACHE	(X1000_CLK_CPU + 1)
+#define X1000_CLK_AHB0		(X1000_CLK_L2CACHE + 1)
+#define X1000_CLK_AHB2PMUX	(X1000_CLK_AHB0 + 1)
+#define X1000_CLK_AHB2		(X1000_CLK_AHB2PMUX + 1)
+#define X1000_CLK_PCLK		(X1000_CLK_AHB2 + 1)
+#define X1000_CLK_DDR		(X1000_CLK_PCLK + 1)
+#define X1000_CLK_MSCMUX	(X1000_CLK_DDR + 1)
+#define X1000_CLK_MSC0		(X1000_CLK_MSCMUX + 1)
+#define X1000_CLK_MSC1		(X1000_CLK_MSC0 + 1)
+#define X1000_CLK_CIMMCLK	(X1000_CLK_MSC1 + 1)
+#define X1000_CLK_PCMPLL	(X1000_CLK_CIMMCLK + 1)
+#define X1000_CLK_PCM		(X1000_CLK_PCMPLL + 1)
+#define X1000_CLK_NEMC		(X1000_CLK_PCM + 1)
+#define X1000_CLK_UART0		(X1000_CLK_NEMC + 1)
+#define X1000_CLK_UART1		(X1000_CLK_UART0 + 1)
+#define X1000_CLK_UART2		(X1000_CLK_UART1 + 1)
+#define X1000_CLK_PDMA		(X1000_CLK_UART2 + 1)
+#define X1000_CLK_CIM		(X1000_CLK_PDMA + 1)
+#define X1000_CLK_DDR0		(X1000_CLK_CIM + 1)
+#define X1000_CLK_DDR1		(X1000_CLK_DDR0 + 1)
+#define X1000_CLK_CORE1		(X1000_CLK_DDR1	+ 1)
+
+#define X1000_CLK_I2SPLL	(X1000_CLK_CORE1 + 1)
+#define X1000_CLK_I2S		(X1000_CLK_I2SPLL + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
-- 
2.10.0

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#1740826 — [RFC 4/4] MIPS: Ingenic: Add Halley2 development board support

Halley2 is a development board from Ingenic using X1000 SoC. It comes
with either 32MB or 64MB of RAM. Add support for halley2 development
board.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 arch/mips/boot/dts/ingenic/Makefile    |  1 +
 arch/mips/boot/dts/ingenic/halley2.dts | 46 +++++++++++++++++++++++++
 arch/mips/configs/halley2_defconfig    | 61 ++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig               |  4 +++
 4 files changed, 112 insertions(+)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/configs/halley2_defconfig

diff --git a/arch/mips/boot/dts/ingenic/Makefile b/arch/mips/boot/dts/ingenic/Makefile
index f2b864f..68e942c 100644
--- a/arch/mips/boot/dts/ingenic/Makefile
+++ b/arch/mips/boot/dts/ingenic/Makefile
@@ -1,5 +1,6 @@
 dtb-$(CONFIG_JZ4740_QI_LB60)	+= qi_lb60.dtb
 dtb-$(CONFIG_JZ4780_CI20)	+= ci20.dtb
+dtb-$(CONFIG_X1000_HALLEY2)	+= halley2.dtb
 
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/ingenic/halley2.dts b/arch/mips/boot/dts/ingenic/halley2.dts
new file mode 100644
index 0000000..9b37119
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/halley2.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "x1000.dtsi"
+
+/ {
+	compatible = "ingenic,halley2", "ingenic,x1000";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+};
+
+&ext {
+	clock-frequency = <24000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
diff --git a/arch/mips/configs/halley2_defconfig b/arch/mips/configs/halley2_defconfig
new file mode 100644
index 0000000..2c49fb7
--- /dev/null
+++ b/arch/mips/configs/halley2_defconfig
@@ -0,0 +1,61 @@
+CONFIG_MACH_INGENIC=y
+CONFIG_X1000_HALLEY2=y
+CONFIG_MACH_X1000=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_8250_INGENIC=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_MEMORY=y
+
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=10
+CONFIG_STACKTRACE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="earlycon console=ttyS2,115200n8 clk_ignore_unused"
+
+CONFIG_HZ_100=y
+CONFIG_HIGHMEM=y
+CONFIG_PREEMPT=y
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=2
+
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+# CONFIG_PM is not set
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 338bc3f..7c66a4b 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -11,6 +11,10 @@ config JZ4780_CI20
 	bool "MIPS Creator CI20"
 	select MACH_JZ4780
 
+config X1000_HALLEY2
+	bool "Ingenic X1000 Halley2 Development board"
+	select MACH_X1000
+
 endchoice
 
 config MACH_JZ4740
-- 
2.10.0

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#1740827 — [RFC 2/4] clk: Add Ingenic X1000 CGU driver

Add support for the clocks provided by CGU in Ingenic X1000 SoC.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 drivers/clk/ingenic/Makefile    |   1 +
 drivers/clk/ingenic/x1000-cgu.c | 203 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 204 insertions(+)
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c

diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index cd47b06..89c665b 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,3 +1,4 @@
 obj-y				+= cgu.o
 obj-$(CONFIG_MACH_JZ4740)	+= jz4740-cgu.o
 obj-$(CONFIG_MACH_JZ4780)	+= jz4780-cgu.o
+obj-$(CONFIG_MACH_X1000)	+= x1000-cgu.o
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
new file mode 100644
index 0000000..a228688
--- /dev/null
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -0,0 +1,203 @@
+/*
+ * Ingenic X1000 SoC CGU driver
+ *
+ * Copyright (c) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include "cgu.h"
+
+/* CGU register offsets */
+#define CGU_REG_CLOCKCONTROL	0x00
+#define CGU_REG_APLL		0x10
+#define CGU_REG_MPLL		0x14
+
+/* CLKGR0, OPCR are not defined in X1000, JZ4780 PM so assuming them to be correct */
+#define CGU_REG_CLKGR0		0x20
+#define CGU_REG_OPCR		0x24
+#define CGU_REG_CLKGR1		0x28
+#define CGU_REG_DDRCDR		0x2c
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0		(1 << 7)
+#define OPCR_SPENDN1		(1 << 6)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[16] = {
+	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+	0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
+};
+
+static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
+
+	/* External clocks */
+
+	[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+	[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+	/* PLLs */
+
+#define DEF_PLL(name) { \
+	.reg = CGU_REG_ ## name, \
+	.m_shift = 19, \
+	.m_bits = 13, \
+	.m_offset = 1, \
+	.n_shift = 13, \
+	.n_bits = 6, \
+	.n_offset = 1, \
+	.od_shift = 9, \
+	.od_bits = 4, \
+	.od_max = 16, \
+	.od_encoding = pll_od_encoding, \
+	.stable_bit = 6, \
+	.bypass_bit = 1, \
+	.enable_bit = 0, \
+}
+
+	[X1000_CLK_APLL] = {
+		"apll", CGU_CLK_PLL,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.pll = DEF_PLL(APLL),
+	},
+
+	[X1000_CLK_MPLL] = {
+		"mpll", CGU_CLK_PLL,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.pll = DEF_PLL(MPLL),
+	},
+
+#undef DEF_PLL
+
+	/* Muxes & dividers */
+
+	[X1000_CLK_SCLKA] = {
+		"sclk_a", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_APLL, X1000_CLK_EXCLK,
+			     X1000_CLK_RTCLK },
+		.mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
+	},
+
+	[X1000_CLK_CPUMUX] = {
+		"cpumux", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     -1 },
+		.mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
+	},
+
+	[X1000_CLK_CPU] = {
+		"cpu", CGU_CLK_DIV,
+		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
+	},
+
+	[X1000_CLK_L2CACHE] = {
+		"l2cache", CGU_CLK_DIV,
+		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
+	},
+
+	[X1000_CLK_AHB0] = {
+		"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     -1 },
+		.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
+		.div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
+	},
+
+	[X1000_CLK_AHB2PMUX] = {
+		"ahb2_apb_mux", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     X1000_CLK_RTCLK },
+		.mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
+	},
+
+	[X1000_CLK_AHB2] = {
+		"ahb2", CGU_CLK_DIV,
+		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
+	},
+
+	[X1000_CLK_PCLK] = {
+		"pclk", CGU_CLK_DIV,
+		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
+	},
+
+	[X1000_CLK_DDR] = {
+		"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+		.mux = { CGU_REG_DDRCDR, 30, 2 },
+		.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+	},
+
+	/* Gate-only clocks */
+
+	[X1000_CLK_UART0] = {
+		"uart0", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 15 },
+	},
+
+	[X1000_CLK_UART1] = {
+		"uart1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 16 },
+	},
+
+	[X1000_CLK_UART2] = {
+		"uart2", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 17 },
+	},
+
+	[X1000_CLK_PDMA] = {
+		"pdma", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 21 },
+	},
+
+	[X1000_CLK_DDR0] = {
+		"ddr0", CGU_CLK_GATE,
+		.parents = { X1000_CLK_DDR, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 30 },
+	},
+
+	[X1000_CLK_DDR1] = {
+		"ddr1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_DDR, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 31 },
+	},
+
+	[X1000_CLK_CORE1] = {
+		"core1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_CPU, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR1, 15 },
+	},
+};
+
+static void __init x1000_cgu_init(struct device_node *np)
+{
+	int retval;
+
+	cgu = ingenic_cgu_new(x1000_cgu_clocks,
+			      ARRAY_SIZE(x1000_cgu_clocks), np);
+	if (!cgu) {
+		pr_err("%s: failed to initialise CGU\n", __func__);
+		return;
+	}
+
+	retval = ingenic_cgu_register_clocks(cgu);
+	if (retval) {
+		pr_err("%s: failed to register CGU Clocks\n", __func__);
+		return;
+	}
+}
+CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
-- 
2.10.0

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