Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1741329 > unrolled thread

Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

Contents

  Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver Vinod Koul <vinod.koul@intel.com> - 2017-09-28 11:30 +0200
    Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver Dmitry Osipenko <digetx@gmail.com> - 2017-09-28 14:30 +0200

#1741329 — Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver

On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:
> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
> modes. This driver is primarily supposed to be used by gpu/host1x in a
> master mode, performing 3D HW context stores.
> 
> Dmitry Osipenko (5):
>   clk: tegra: Add AHB DMA clock entry
>   clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
>   dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
>   dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
>   ARM: dts: tegra: Add AHB DMA controller nodes

I don't think they are dependent, so consider sending them separately

-- 
~Vinod

[toc] | [next] | [standalone]

#1741494

On 28.09.2017 12:31, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:
>> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
>> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
>> modes. This driver is primarily supposed to be used by gpu/host1x in a
>> master mode, performing 3D HW context stores.
>>
>> Dmitry Osipenko (5):
>>   clk: tegra: Add AHB DMA clock entry
>>   clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
>>   dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
>>   dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
>>   ARM: dts: tegra: Add AHB DMA controller nodes
> 
> I don't think they are dependent, so consider sending them separately
> 

Well, they are dependent in a sense of making driver usable. Only the "SCLK rate
bump" patch isn't strictly needed.

Splitting this series won't cause building failures, but all pieces should be in
place for the working driver. So I suppose it is okay if clk patches would get
in earlier than the others, I'll split the series.

Thank you for the review.

-- 
Dmitry

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web