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| Started by | Vinod Koul <vinod.koul@intel.com> |
|---|---|
| First post | 2017-09-25 08:20 +0200 |
| Last post | 2017-09-25 09:00 +0200 |
| Articles | 2 — 2 participants |
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Re: [PATCH v4] dmaengine: qcom-bam: Process multiple pending descriptors Vinod Koul <vinod.koul@intel.com> - 2017-09-25 08:20 +0200
Re: [PATCH v4] dmaengine: qcom-bam: Process multiple pending descriptors Sricharan R <sricharan@codeaurora.org> - 2017-09-25 09:00 +0200
| From | Vinod Koul <vinod.koul@intel.com> |
|---|---|
| Date | 2017-09-25 08:20 +0200 |
| Subject | Re: [PATCH v4] dmaengine: qcom-bam: Process multiple pending descriptors |
| Message-ID | <utuUh-2ui-3@gated-at.bofh.it> |
On Mon, Aug 28, 2017 at 08:30:24PM +0530, Sricharan R wrote: > The bam dmaengine has a circular FIFO to which we > add hw descriptors that describes the transaction. > The FIFO has space for about 4096 hw descriptors. > > Currently we add one descriptor and wait for it to > complete with interrupt and then add the next pending > descriptor. In this way, the FIFO is underutilized > since only one descriptor is processed at a time, although > there is space in FIFO for the BAM to process more. > > Instead keep adding descriptors to FIFO till its full, > that allows BAM to continue to work on the next descriptor > immediately after signalling completion interrupt for the > previous descriptor. > > Also when the client has not set the DMA_PREP_INTERRUPT for > a descriptor, then do not configure BAM to trigger a interrupt > upon completion of that descriptor. This way we get a interrupt > only for the descriptor for which DMA_PREP_INTERRUPT was > requested and there signal completion of all the previous completed > descriptors. So we still do callbacks for all requested descriptors, > but just that the number of interrupts are reduced. > > CURRENT: > > ------ ------- --------------- > |DES 0| |DESC 1| |DESC 2 + INT | > ------ ------- --------------- > | | | > | | | > INTERRUPT: (INT) (INT) (INT) > CALLBACK: (CB) (CB) (CB) > > MTD_SPEEDTEST READ PAGE: 3560 KiB/s > MTD_SPEEDTEST WRITE PAGE: 2664 KiB/s > IOZONE READ: 2456 KB/s > IOZONE WRITE: 1230 KB/s > > bam dma interrupts (after tests): 96508 > > CHANGE: > > ------ ------- ------------- > |DES 0| |DESC 1 |DESC 2 + INT | > ------ ------- -------------- > | > | > (INT) > (CB for 0, 1, 2) > > MTD_SPEEDTEST READ PAGE: 3860 KiB/s > MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s > IOZONE READ: 2677 KB/s > IOZONE WRITE: 1308 KB/s > > bam dma interrupts (after tests): 58806 Applied, thanks. Sorry for the delay, bad timing I guess :) -- ~Vinod
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| From | Sricharan R <sricharan@codeaurora.org> |
|---|---|
| Date | 2017-09-25 09:00 +0200 |
| Message-ID | <utvx0-2Kk-5@gated-at.bofh.it> |
| In reply to | #1738755 |
On 9/25/2017 11:50 AM, Vinod Koul wrote: > On Mon, Aug 28, 2017 at 08:30:24PM +0530, Sricharan R wrote: >> The bam dmaengine has a circular FIFO to which we >> add hw descriptors that describes the transaction. >> The FIFO has space for about 4096 hw descriptors. >> >> Currently we add one descriptor and wait for it to >> complete with interrupt and then add the next pending >> descriptor. In this way, the FIFO is underutilized >> since only one descriptor is processed at a time, although >> there is space in FIFO for the BAM to process more. >> >> Instead keep adding descriptors to FIFO till its full, >> that allows BAM to continue to work on the next descriptor >> immediately after signalling completion interrupt for the >> previous descriptor. >> >> Also when the client has not set the DMA_PREP_INTERRUPT for >> a descriptor, then do not configure BAM to trigger a interrupt >> upon completion of that descriptor. This way we get a interrupt >> only for the descriptor for which DMA_PREP_INTERRUPT was >> requested and there signal completion of all the previous completed >> descriptors. So we still do callbacks for all requested descriptors, >> but just that the number of interrupts are reduced. >> >> CURRENT: >> >> ------ ------- --------------- >> |DES 0| |DESC 1| |DESC 2 + INT | >> ------ ------- --------------- >> | | | >> | | | >> INTERRUPT: (INT) (INT) (INT) >> CALLBACK: (CB) (CB) (CB) >> >> MTD_SPEEDTEST READ PAGE: 3560 KiB/s >> MTD_SPEEDTEST WRITE PAGE: 2664 KiB/s >> IOZONE READ: 2456 KB/s >> IOZONE WRITE: 1230 KB/s >> >> bam dma interrupts (after tests): 96508 >> >> CHANGE: >> >> ------ ------- ------------- >> |DES 0| |DESC 1 |DESC 2 + INT | >> ------ ------- -------------- >> | >> | >> (INT) >> (CB for 0, 1, 2) >> >> MTD_SPEEDTEST READ PAGE: 3860 KiB/s >> MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s >> IOZONE READ: 2677 KB/s >> IOZONE WRITE: 1308 KB/s >> >> bam dma interrupts (after tests): 58806 > > Applied, thanks. > > Sorry for the delay, bad timing I guess :) > Sure np, Thanks for that. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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