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[PATCH v3 0/5] K2G: Add QSPI support

Started byVignesh R <vigneshr@ti.com>
First post2017-09-24 13:10 +0200
Last post2017-09-24 13:10 +0200
Articles 6 — 2 participants

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Contents

  [PATCH v3 0/5] K2G: Add QSPI support Vignesh R <vigneshr@ti.com> - 2017-09-24 13:10 +0200
    [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R <vigneshr@ti.com> - 2017-09-24 13:10 +0200
      Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in  write sequence Marek Vasut <marek.vasut@gmail.com> - 2017-09-24 14:20 +0200
        Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in  write sequence Vignesh R <vigneshr@ti.com> - 2017-09-24 14:40 +0200
          Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in  write sequence Marek Vasut <marek.vasut@gmail.com> - 2017-09-24 15:20 +0200
    [PATCH v3 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R <vigneshr@ti.com> - 2017-09-24 13:10 +0200

#1738150 — [PATCH v3 0/5] K2G: Add QSPI support

FromVignesh R <vigneshr@ti.com>
Date2017-09-24 13:10 +0200
Subject[PATCH v3 0/5] K2G: Add QSPI support
Message-ID<utcXo-7Yz-5@gated-at.bofh.it>
This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
The patches enhance the existing cadence-quadspi driver to support
loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.

Change log:

v3:
* Fix build warnings reported by kbuild test bot.

Resend:
* Rebase to latest linux-next.
* Collect Acked-bys

v2:
* Drop DT patches. Will be sent as separate series as requested by
 maintainer.
* Split binding docs into separate patches.
* Address comments by Rob Herring.


Vignesh R (5):
  mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
    circuit
  mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
    circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support

 .../devicetree/bindings/mtd/cadence-quadspi.txt    |  7 +++-
 drivers/mtd/spi-nor/cadence-quadspi.c              | 46 ++++++++++++++++++++--
 2 files changed, 49 insertions(+), 4 deletions(-)

-- 
2.14.1

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#1738152 — [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

FromVignesh R <vigneshr@ti.com>
Date2017-09-24 13:10 +0200
Subject[PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
Message-ID<utcXo-7Yz-25@gated-at.bofh.it>
In reply to#1738150
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
---

v3:
Fix build warnings reported by kbuild test bot.

 drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..5cd5d6f7303f 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -38,6 +38,9 @@
 #define CQSPI_NAME			"cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT		16
 
+/* Quirks */
+#define CQSPI_NEEDS_WR_DELAY		BIT(0)
+
 struct cqspi_st;
 
 struct cqspi_flash_pdata {
@@ -76,6 +79,7 @@ struct cqspi_st {
 	u32			fifo_depth;
 	u32			fifo_width;
 	u32			trigger_address;
+	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTWR);
+	/*
+	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+	 * Controller programming sequence, couple of cycles of
+	 * QSPI_REF_CLK delay is required for the above bit to
+	 * be internally synchronized by the QSPI module. Provide 5
+	 * cycles of delay.
+	 */
+	if (cqspi->wr_delay)
+		ndelay(cqspi->wr_delay);
 
 	while (remaining > 0) {
 		write_bytes = remaining > page_size ? page_size : remaining;
@@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	struct resource *res;
 	struct resource *res_ahb;
+	unsigned long data;
 	int ret;
 	int irq;
 
@@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+	data  = (unsigned long)of_device_get_match_data(dev);
+	if (data & CQSPI_NEEDS_WR_DELAY)
+		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+						   cqspi->master_ref_clk_hz);
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
 			       pdev->name, cqspi);
@@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 #endif
 
 static const struct of_device_id cqspi_dt_ids[] = {
-	{.compatible = "cdns,qspi-nor",},
+	{
+		.compatible = "cdns,qspi-nor",
+		.data = (void *)0,
+	},
+	{
+		.compatible = "ti,k2g-qspi",
+		.data = (void *)CQSPI_NEEDS_WR_DELAY,
+	},
 	{ /* end of table */ }
 };
 
-- 
2.14.1

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#1738173 — Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

FromMarek Vasut <marek.vasut@gmail.com>
Date2017-09-24 14:20 +0200
SubjectRe: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
Message-ID<ute38-as-1@gated-at.bofh.it>
In reply to#1738152
On 09/24/2017 12:59 PM, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple of QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
> to handle this and set this flag for TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Is this TI specific or is this controller property ? I wouldn't be
surprised of the later ...

> ---
> 
> v3:
> Fix build warnings reported by kbuild test bot.
> 
>  drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 53c7d8e0327a..5cd5d6f7303f 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -38,6 +38,9 @@
>  #define CQSPI_NAME			"cadence-qspi"
>  #define CQSPI_MAX_CHIPSELECT		16
>  
> +/* Quirks */
> +#define CQSPI_NEEDS_WR_DELAY		BIT(0)
> +
>  struct cqspi_st;
>  
>  struct cqspi_flash_pdata {
> @@ -76,6 +79,7 @@ struct cqspi_st {
>  	u32			fifo_depth;
>  	u32			fifo_width;
>  	u32			trigger_address;
> +	u32			wr_delay;
>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>  };
>  
> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  	reinit_completion(&cqspi->transfer_complete);
>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>  	       reg_base + CQSPI_REG_INDIRECTWR);
> +	/*
> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
> +	 * Controller programming sequence, couple of cycles of
> +	 * QSPI_REF_CLK delay is required for the above bit to
> +	 * be internally synchronized by the QSPI module. Provide 5
> +	 * cycles of delay.
> +	 */
> +	if (cqspi->wr_delay)
> +		ndelay(cqspi->wr_delay);
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
>  	struct cqspi_st *cqspi;
>  	struct resource *res;
>  	struct resource *res_ahb;
> +	unsigned long data;
>  	int ret;
>  	int irq;
>  
> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
>  	}
>  
>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +	data  = (unsigned long)of_device_get_match_data(dev);
> +	if (data & CQSPI_NEEDS_WR_DELAY)
> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> +						   cqspi->master_ref_clk_hz);
>  
>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>  			       pdev->name, cqspi);
> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>  #endif
>  
>  static const struct of_device_id cqspi_dt_ids[] = {
> -	{.compatible = "cdns,qspi-nor",},
> +	{
> +		.compatible = "cdns,qspi-nor",
> +		.data = (void *)0,
> +	},
> +	{
> +		.compatible = "ti,k2g-qspi",
> +		.data = (void *)CQSPI_NEEDS_WR_DELAY,
> +	},
>  	{ /* end of table */ }
>  };
>  
> 


-- 
Best regards,
Marek Vasut

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#1738179 — Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

FromVignesh R <vigneshr@ti.com>
Date2017-09-24 14:40 +0200
SubjectRe: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
Message-ID<utemu-gn-3@gated-at.bofh.it>
In reply to#1738173

On 9/24/2017 5:29 PM, Marek Vasut wrote:
> On 09/24/2017 12:59 PM, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple of QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
>> to handle this and set this flag for TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
> 
> Is this TI specific or is this controller property ? I wouldn't be
> surprised of the later ...

I am not sure, there is no generic public documentation by cadence for
this IP. TI TRM clearly states this delay is required and I have
verified it practically that this delay is indeed needed.
But current user of this IP, socfpga does not seem to mention anything
about it. So, I guess its TI specific quirk.

> 
>> ---
>>
>> v3:
>> Fix build warnings reported by kbuild test bot.
>>
>>  drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 53c7d8e0327a..5cd5d6f7303f 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -38,6 +38,9 @@
>>  #define CQSPI_NAME			"cadence-qspi"
>>  #define CQSPI_MAX_CHIPSELECT		16
>>  
>> +/* Quirks */
>> +#define CQSPI_NEEDS_WR_DELAY		BIT(0)
>> +
>>  struct cqspi_st;
>>  
>>  struct cqspi_flash_pdata {
>> @@ -76,6 +79,7 @@ struct cqspi_st {
>>  	u32			fifo_depth;
>>  	u32			fifo_width;
>>  	u32			trigger_address;
>> +	u32			wr_delay;
>>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>>  };
>>  
>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>>  	reinit_completion(&cqspi->transfer_complete);
>>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>>  	       reg_base + CQSPI_REG_INDIRECTWR);
>> +	/*
>> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
>> +	 * Controller programming sequence, couple of cycles of
>> +	 * QSPI_REF_CLK delay is required for the above bit to
>> +	 * be internally synchronized by the QSPI module. Provide 5
>> +	 * cycles of delay.
>> +	 */
>> +	if (cqspi->wr_delay)
>> +		ndelay(cqspi->wr_delay);
>>  
>>  	while (remaining > 0) {
>>  		write_bytes = remaining > page_size ? page_size : remaining;
>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	struct cqspi_st *cqspi;
>>  	struct resource *res;
>>  	struct resource *res_ahb;
>> +	unsigned long data;
>>  	int ret;
>>  	int irq;
>>  
>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	}
>>  
>>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>> +	data  = (unsigned long)of_device_get_match_data(dev);
>> +	if (data & CQSPI_NEEDS_WR_DELAY)
>> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>> +						   cqspi->master_ref_clk_hz);
>>  
>>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>>  			       pdev->name, cqspi);
>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>>  #endif
>>  
>>  static const struct of_device_id cqspi_dt_ids[] = {
>> -	{.compatible = "cdns,qspi-nor",},
>> +	{
>> +		.compatible = "cdns,qspi-nor",
>> +		.data = (void *)0,
>> +	},
>> +	{
>> +		.compatible = "ti,k2g-qspi",
>> +		.data = (void *)CQSPI_NEEDS_WR_DELAY,
>> +	},
>>  	{ /* end of table */ }
>>  };
>>  
>>
> 
>

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#1738186 — Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

FromMarek Vasut <marek.vasut@gmail.com>
Date2017-09-24 15:20 +0200
SubjectRe: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
Message-ID<uteZc-JV-11@gated-at.bofh.it>
In reply to#1738179
On 09/24/2017 02:33 PM, Vignesh R wrote:
> 
> 
> On 9/24/2017 5:29 PM, Marek Vasut wrote:
>> On 09/24/2017 12:59 PM, Vignesh R wrote:
>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>>> Controller programming sequence, a delay equal to couple of QSPI master
>>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
>>> to handle this and set this flag for TI 66AK2G SoC.
>>>
>>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>>
>>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>>
>> Is this TI specific or is this controller property ? I wouldn't be
>> surprised of the later ...
> 
> I am not sure, there is no generic public documentation by cadence for
> this IP. TI TRM clearly states this delay is required and I have
> verified it practically that this delay is indeed needed.
> But current user of this IP, socfpga does not seem to mention anything
> about it. So, I guess its TI specific quirk.

OK, let's go with that then. I didn't observe any stability issues with
SoCFPGA, but I didn't run the flash at 100s of MHz either. At what kind
of frequencies does the quirk become relevant ?

>>
>>> ---
>>>
>>> v3:
>>> Fix build warnings reported by kbuild test bot.
>>>
>>>  drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
>>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>>> index 53c7d8e0327a..5cd5d6f7303f 100644
>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>>> @@ -38,6 +38,9 @@
>>>  #define CQSPI_NAME			"cadence-qspi"
>>>  #define CQSPI_MAX_CHIPSELECT		16
>>>  
>>> +/* Quirks */
>>> +#define CQSPI_NEEDS_WR_DELAY		BIT(0)
>>> +
>>>  struct cqspi_st;
>>>  
>>>  struct cqspi_flash_pdata {
>>> @@ -76,6 +79,7 @@ struct cqspi_st {
>>>  	u32			fifo_depth;
>>>  	u32			fifo_width;
>>>  	u32			trigger_address;
>>> +	u32			wr_delay;
>>>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>>>  };
>>>  
>>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>>>  	reinit_completion(&cqspi->transfer_complete);
>>>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>>>  	       reg_base + CQSPI_REG_INDIRECTWR);
>>> +	/*
>>> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
>>> +	 * Controller programming sequence, couple of cycles of
>>> +	 * QSPI_REF_CLK delay is required for the above bit to
>>> +	 * be internally synchronized by the QSPI module. Provide 5
>>> +	 * cycles of delay.
>>> +	 */
>>> +	if (cqspi->wr_delay)
>>> +		ndelay(cqspi->wr_delay);
>>>  
>>>  	while (remaining > 0) {
>>>  		write_bytes = remaining > page_size ? page_size : remaining;
>>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
>>>  	struct cqspi_st *cqspi;
>>>  	struct resource *res;
>>>  	struct resource *res_ahb;
>>> +	unsigned long data;
>>>  	int ret;
>>>  	int irq;
>>>  
>>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
>>>  	}
>>>  
>>>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>>> +	data  = (unsigned long)of_device_get_match_data(dev);
>>> +	if (data & CQSPI_NEEDS_WR_DELAY)
>>> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>>> +						   cqspi->master_ref_clk_hz);
>>>  
>>>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>>>  			       pdev->name, cqspi);
>>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>>>  #endif
>>>  
>>>  static const struct of_device_id cqspi_dt_ids[] = {
>>> -	{.compatible = "cdns,qspi-nor",},
>>> +	{
>>> +		.compatible = "cdns,qspi-nor",
>>> +		.data = (void *)0,
>>> +	},
>>> +	{
>>> +		.compatible = "ti,k2g-qspi",
>>> +		.data = (void *)CQSPI_NEEDS_WR_DELAY,
>>> +	},
>>>  	{ /* end of table */ }
>>>  };
>>>  
>>>
>>
>>


-- 
Best regards,
Marek Vasut

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#1738153 — [PATCH v3 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible

FromVignesh R <vigneshr@ti.com>
Date2017-09-24 13:10 +0200
Subject[PATCH v3 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
Message-ID<utcXp-7Yz-33@gated-at.bofh.it>
In reply to#1738150
Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..7dbe3bd9ac56 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
 * Cadence Quad SPI controller
 
 Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+	Generic default - "cdns,qspi-nor".
+	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
 - reg : Contains two entries, each of which is a tuple consisting of a
 	physical address and length. The first entry is the address and
 	length of the controller register set. The second entry is the
-- 
2.14.1

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