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| Started by | Nickey Yang <nickey.yang@rock-chips.com> |
|---|---|
| First post | 2017-09-26 10:00 +0200 |
| Last post | 2017-09-26 16:10 +0200 |
| Articles | 2 — 2 participants |
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[PATCH v2 7/8] arm64: dts: rockchip: add a grf clk for dw-mipi-dsi Nickey Yang <nickey.yang@rock-chips.com> - 2017-09-26 10:00 +0200
Re: [PATCH v2 7/8] arm64: dts: rockchip: add a grf clk for dw-mipi-dsi Heiko Stuebner <heiko@sntech.de> - 2017-09-26 16:10 +0200
| From | Nickey Yang <nickey.yang@rock-chips.com> |
|---|---|
| Date | 2017-09-26 10:00 +0200 |
| Subject | [PATCH v2 7/8] arm64: dts: rockchip: add a grf clk for dw-mipi-dsi |
| Message-ID | <utSWC-1N5-3@gated-at.bofh.it> |
The clk of grf must be enabled before writing grf register for rk3399. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6aa43fd..ab7629c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1630,8 +1630,8 @@ reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>; - clock-names = "ref", "pclk", "phy_cfg"; + <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; power-domains = <&power RK3399_PD_VIO>; rockchip,grf = <&grf>; status = "disabled"; -- 1.9.1
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| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2017-09-26 16:10 +0200 |
| Message-ID | <utYIG-5O1-17@gated-at.bofh.it> |
| In reply to | #1739640 |
Am Dienstag, 26. September 2017, 15:55:22 CEST schrieb Nickey Yang: > The clk of grf must be enabled before writing grf > register for rk3399. > > Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> applied as fix for 4.14 Thanks Heiko
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