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Groups > linux.kernel > #1736069 > unrolled thread
| Started by | Jernej Skrabec <jernej.skrabec@siol.net> |
|---|---|
| First post | 2017-09-20 22:10 +0200 |
| Last post | 2017-09-21 12:00 +0200 |
| Articles | 4 — 3 participants |
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[RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI Jernej Skrabec <jernej.skrabec@siol.net> - 2017-09-20 22:10 +0200
[RESEND RFC PATCH 4/7] dt-bindings: Document Allwinner DWC HDMI TX node Jernej Skrabec <jernej.skrabec@siol.net> - 2017-09-20 22:10 +0200
Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI Jose Abreu <Jose.Abreu@synopsys.com> - 2017-09-21 11:50 +0200
Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI Hans Verkuil <hansverk@cisco.com> - 2017-09-21 12:00 +0200
| From | Jernej Skrabec <jernej.skrabec@siol.net> |
|---|---|
| Date | 2017-09-20 22:10 +0200 |
| Subject | [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI |
| Message-ID | <urTtL-7M2-3@gated-at.bofh.it> |
[added media mailing list due to CEC question] This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only video and CEC functionality is supported. Audio needs more tweaks. Series is based on the H3 DE2 patch series available on mailing list: http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html (ignore patches marked with [NOT FOR REVIEW NOW] tag) Patch 1 adds support for polling plug detection since custom PHY used here doesn't support HPD interrupt. Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits same issues as HDMI controller used in iMX6 SoCs. Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock. Patch 4 adds dt bindings documentation. Patch 5 adds actual H3 HDMI glue driver. Patch 6 and 7 add HDMI node to DT and enable it where needed. Allwinner used DW HDMI controller in a non standard way: - register offsets obfuscation layer, which can fortunately be turned off - register read lock, which has to be disabled by magic number - custom PHY, which have to be initialized before DW HDMI controller - non standard clocks - no HPD interrupt Because of that, I have two questions: - Since HPD have to be polled, is it enough just to enable poll mode? I'm mainly concerned about invalidating CEC address here. - PHY has to be initialized before DW HDMI controller to disable offset obfuscation and read lock among other things. This means that all clocks have to be enabled in glue driver. This poses a problem, since when using component model, dw-hdmi bridge uses drvdata for it's own private data and prevents glue layer to pass a pointer to unbind function, where clocks should be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks are also not disabled when unbind callback is called. I noticed that when H3 SoC is shutdown, HDMI output is still enabled and lastest image is shown on monitor until it is unplugged from power supply. Is there any simple solution to this? Chen-Yu, TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think it is safe to assume that divider in HDMI clock doesn't have any effect. Branch based on linux-next from 1. September with integrated patches is available here: https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc Some additonal info about H3 HDMI: https://linux-sunxi.org/DWC_HDMI_Controller Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller and mapped scrambled register offsets to original ones. Icenowy Zheng (1): ARM: sun8i: h3: Add DesignWare HDMI controller node Jernej Skrabec (6): drm: bridge: Enable polling hpd event in dw_hdmi drm: bridge: Enable workaround in dw_hdmi for v1.32a clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock dt-bindings: Document Allwinner DWC HDMI TX node drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 ARM: sun8i: h3: Enable HDMI output on H3 boards .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 33 ++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 33 ++ arch/arm/boot/dts/sun8i-h3.dtsi | 5 + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 36 ++ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +- drivers/gpu/drm/sun4i/Kconfig | 9 + drivers/gpu/drm/sun4i/Makefile | 1 + drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 500 +++++++++++++++++++++ 15 files changed, 950 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -- 2.14.1
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| From | Jernej Skrabec <jernej.skrabec@siol.net> |
|---|---|
| Date | 2017-09-20 22:10 +0200 |
| Subject | [RESEND RFC PATCH 4/7] dt-bindings: Document Allwinner DWC HDMI TX node |
| Message-ID | <urTtM-7M2-27@gated-at.bofh.it> |
| In reply to | #1736069 |
Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++++++++++++++++-
1 file changed, 157 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 92512953943e..cb6aee5c486f 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -60,6 +60,40 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+DWC HDMI TX Encoder
+-----------------------------
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
+Required properties:
+
+ - compatible: value must be one of:
+ * "allwinner,sun8i-h3-dw-hdmi"
+ - reg: two pairs of base address and size of memory-mapped region, first
+ for controller and second for PHY
+ registers.
+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
+ - interrupts: HDMI interrupt number
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * iahb: the HDMI interface clock
+ * isfr: the HDMI module clock
+ * ddc: the HDMI ddc clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset controllers driving the encoder
+ * hdmi: the reset line for the HDMI
+ * ddc: the reset line for the DDC
+ - reset-names: the reset names mentioned above
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
TV Encoder
----------
@@ -255,7 +289,7 @@ Required properties:
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
-Example:
+Example 1:
panel: panel {
compatible = "olimex,lcd-olinuxino-43-ts";
@@ -455,3 +489,125 @@ display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
+
+Example 2:
+
+connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+};
+
+de: display-engine {
+ compatible = "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <&mixer0>;
+};
+
+hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,h3-dw-hdmi";
+ reg = <0x01ee0000 0x10000>,
+ <0x01ef0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu CLK_HDMI_DDC>;
+ clock-names = "iahb", "isfr", "ddc";
+ resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
+ reset-names = "hdmi", "ddc";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
+
+mixer0: mixer@1100000 {
+ compatible = "allwinner,sun8i-h3-de2-mixer0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+ };
+ };
+};
+
+tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-h3-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>,
+ <&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ };
+ };
+ };
+};
--
2.14.1
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| From | Jose Abreu <Jose.Abreu@synopsys.com> |
|---|---|
| Date | 2017-09-21 11:50 +0200 |
| Message-ID | <us6hl-7zm-27@gated-at.bofh.it> |
| In reply to | #1736069 |
Hi Jernej,
On 20-09-2017 21:01, Jernej Skrabec wrote:
> [added media mailing list due to CEC question]
>
> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only
> video and CEC functionality is supported. Audio needs more tweaks.
>
> Series is based on the H3 DE2 patch series available on mailing list:
> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e=
> (ignore patches marked with [NOT FOR REVIEW NOW] tag)
>
> Patch 1 adds support for polling plug detection since custom PHY used here
> doesn't support HPD interrupt.
>
> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits
> same issues as HDMI controller used in iMX6 SoCs.
>
> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.
>
> Patch 4 adds dt bindings documentation.
>
> Patch 5 adds actual H3 HDMI glue driver.
>
> Patch 6 and 7 add HDMI node to DT and enable it where needed.
>
> Allwinner used DW HDMI controller in a non standard way:
> - register offsets obfuscation layer, which can fortunately be turned off
> - register read lock, which has to be disabled by magic number
> - custom PHY, which have to be initialized before DW HDMI controller
> - non standard clocks
> - no HPD interrupt
>
> Because of that, I have two questions:
> - Since HPD have to be polled, is it enough just to enable poll mode? I'm
> mainly concerned about invalidating CEC address here.
You mean you get no interrupt when HPD status changes? Hans can
answer this better but then you will need to invalidate the cec
physical address yourself because right now its invalidated in
the dw-hdmi irq handler (see dw_hdmi_irq()).
> - PHY has to be initialized before DW HDMI controller to disable offset
> obfuscation and read lock among other things. This means that all clocks have
> to be enabled in glue driver. This poses a problem, since when using
> component model, dw-hdmi bridge uses drvdata for it's own private data and
> prevents glue layer to pass a pointer to unbind function, where clocks should
> be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks
> are also not disabled when unbind callback is called. I noticed that when H3
> SoC is shutdown, HDMI output is still enabled and lastest image is shown on
> monitor until it is unplugged from power supply. Is there any simple solution
> to this?
I don't know if you can use an empty platform device created with
platform_device_alloc(). Perhaps it would be better fix this in
the dw-hdmi driver. I see two solutions:
- Either you return the dw-hdmi private structure in the bind
callback, store it and pass it in the unbind
- Or, you pass your own private data to the dw-hdmi bind, the
dw-hdmi stores it and you just create a public function in the
dw-hdmi driver called like dw_hdmi_get_auxdata(struct device
*dev) which returns your private data.
I think first option is nice, maybe anyone else can suggest
something better?
Best regards,
Jose Miguel Abreu
>
> Chen-Yu,
> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think
> it is safe to assume that divider in HDMI clock doesn't have any effect.
>
> Branch based on linux-next from 1. September with integrated patches is
> available here:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_jernejsk_linux-2D1_tree_h3-5Fhdmi-5Frfc&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=lDAnd3egsc2sxqVM-Ya_Me9ozWXKWvxxvsdV3Jn3vpA&e=
>
> Some additonal info about H3 HDMI:
> https://urldefense.proofpoint.com/v2/url?u=https-3A__linux-2Dsunxi.org_DWC-5FHDMI-5FController&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=d9iEgk23RCLJL4oXJ4kkt6NyYK90_vFy0mCD3WauJDk&e=
>
> Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller
> and mapped scrambled register offsets to original ones.
>
> Icenowy Zheng (1):
> ARM: sun8i: h3: Add DesignWare HDMI controller node
>
> Jernej Skrabec (6):
> drm: bridge: Enable polling hpd event in dw_hdmi
> drm: bridge: Enable workaround in dw_hdmi for v1.32a
> clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
> dt-bindings: Document Allwinner DWC HDMI TX node
> drm: sun4i: Add a glue for the DesignWare HDMI controller in H3
> ARM: sun8i: h3: Enable HDMI output on H3 boards
>
> .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++-
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 33 ++
> arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 36 ++
> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +-
> drivers/gpu/drm/sun4i/Kconfig | 9 +
> drivers/gpu/drm/sun4i/Makefile | 1 +
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 500 +++++++++++++++++++++
> 15 files changed, 950 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>
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| From | Hans Verkuil <hansverk@cisco.com> |
|---|---|
| Date | 2017-09-21 12:00 +0200 |
| Message-ID | <us6qZ-7Dh-1@gated-at.bofh.it> |
| In reply to | #1736503 |
On 09/21/17 11:39, Jose Abreu wrote: > Hi Jernej, > > On 20-09-2017 21:01, Jernej Skrabec wrote: >> [added media mailing list due to CEC question] >> >> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only >> video and CEC functionality is supported. Audio needs more tweaks. >> >> Series is based on the H3 DE2 patch series available on mailing list: >> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e= >> (ignore patches marked with [NOT FOR REVIEW NOW] tag) >> >> Patch 1 adds support for polling plug detection since custom PHY used here >> doesn't support HPD interrupt. >> >> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits >> same issues as HDMI controller used in iMX6 SoCs. >> >> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock. >> >> Patch 4 adds dt bindings documentation. >> >> Patch 5 adds actual H3 HDMI glue driver. >> >> Patch 6 and 7 add HDMI node to DT and enable it where needed. >> >> Allwinner used DW HDMI controller in a non standard way: >> - register offsets obfuscation layer, which can fortunately be turned off >> - register read lock, which has to be disabled by magic number >> - custom PHY, which have to be initialized before DW HDMI controller >> - non standard clocks >> - no HPD interrupt >> >> Because of that, I have two questions: >> - Since HPD have to be polled, is it enough just to enable poll mode? I'm >> mainly concerned about invalidating CEC address here. > > You mean you get no interrupt when HPD status changes? Hans can > answer this better but then you will need to invalidate the cec > physical address yourself because right now its invalidated in > the dw-hdmi irq handler (see dw_hdmi_irq()). That's correct. When the HPD goes low you need to call cec_notifier_phys_addr_invalidate() to invalidate the physical address. This is not terribly time sensitive, i.e. checking this once a second would be quick enough. Regards, Hans
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