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Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers

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  Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers Linus Walleij <linus.walleij@linaro.org> - 2017-09-14 16:00 +0200
    Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers Tony Lindgren <tony@atomide.com> - 2017-09-15 01:40 +0200
      Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers Tony Lindgren <tony@atomide.com> - 2017-09-15 01:50 +0200

#1732287 — Re: [PATCH 14/16] gpio: Add support for banked GPIO controllers

On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> Some GPIO controllers are subdivided into multiple logical blocks called
> banks (or ports). This is often caused by the design assigning separate
> resources, such as register regions or interrupts, to each bank, or some
> set of banks.
>
> This commit adds support for describing controllers that have such a
> banked design and provides common code for dealing with them.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

This patch makes me really happy.

It pulls in a lot of weirdness to the OF core and creates a coherent
way of handling these "banked" GPIO chips.

CC to Tony to make sure he checks that OMAP is ready to use this
too.

I would change num_pins to num_lines everywhere in this patch,
so if you resend the series, please fix that.

> +void gpio_irq_chip_banked_handler(struct irq_desc *desc)

Maybe we should name this gpio_irq_chip_banked_chained_handler()
since it only deals with chained IRQs?

Sooner or later we will have a nested bank too...

Otherwise it looks fine.

Yours,
Linus Walleij

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#1732646

* Linus Walleij <linus.walleij@linaro.org> [170914 07:00]:
> On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Some GPIO controllers are subdivided into multiple logical blocks called
> > banks (or ports). This is often caused by the design assigning separate
> > resources, such as register regions or interrupts, to each bank, or some
> > set of banks.
> >
> > This commit adds support for describing controllers that have such a
> > banked design and provides common code for dealing with them.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> 
> This patch makes me really happy.
> 
> It pulls in a lot of weirdness to the OF core and creates a coherent
> way of handling these "banked" GPIO chips.
> 
> CC to Tony to make sure he checks that OMAP is ready to use this
> too.

Adding Grygorii to Cc as well, we'll take a look.

Probably the runtime PM will be an issue here still. We must currently
do runtime PM on per GPIO bank basis instead of per GPIO pin level as
we constantly runtime_suspend/resume the whole GPIO bank for idle modes
on the SoCs that support PM. So the usage count for the bank needs to
be either 0 or 1 and cannot be the lines used in the bank.

Regards,

Tony

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#1732647

* Tony Lindgren <tony@atomide.com> [170914 16:38]:
> * Linus Walleij <linus.walleij@linaro.org> [170914 07:00]:
> > On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding <thierry.reding@gmail.com> wrote:
> > 
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Some GPIO controllers are subdivided into multiple logical blocks called
> > > banks (or ports). This is often caused by the design assigning separate
> > > resources, such as register regions or interrupts, to each bank, or some
> > > set of banks.
> > >
> > > This commit adds support for describing controllers that have such a
> > > banked design and provides common code for dealing with them.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > 
> > This patch makes me really happy.
> > 
> > It pulls in a lot of weirdness to the OF core and creates a coherent
> > way of handling these "banked" GPIO chips.
> > 
> > CC to Tony to make sure he checks that OMAP is ready to use this
> > too.
> 
> Adding Grygorii to Cc as well, we'll take a look.
> 
> Probably the runtime PM will be an issue here still. We must currently
> do runtime PM on per GPIO bank basis instead of per GPIO pin level as
> we constantly runtime_suspend/resume the whole GPIO bank for idle modes
> on the SoCs that support PM. So the usage count for the bank needs to
> be either 0 or 1 and cannot be the lines used in the bank.

And based on a quick look at this series it should not cause
problems there. For managing the banks in a generic way, I
like the idea too.

Regards,

Tony

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