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[PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

Started by"Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com>
First post2017-09-14 18:10 +0200
Last post2017-09-15 04:20 +0200
Articles 3 — 2 participants

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  [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when  adjustin CPUX clock on A33 "Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com> - 2017-09-14 18:10 +0200
    Re: [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when  adjustin CPUX clock on A33 icenowy@aosc.io - 2017-09-15 04:10 +0200
      Re: [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when  adjustin CPUX clock on A33 "Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com> - 2017-09-15 04:20 +0200

#1732397 — [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

From"Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com>
Date2017-09-14 18:10 +0200
Subject[PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
Message-ID<upESd-7ea-1@gated-at.bofh.it>
From: Icenowy Zheng <icenowy@aosc.xyz>

[ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ]

The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 9bd1f78a0547..d54e5db3959a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 					     "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-		     0x050, 16, 2, CLK_IS_CRITICAL);
+		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
-- 
2.11.0

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#1732677

Fromicenowy@aosc.io
Date2017-09-15 04:10 +0200
Message-ID<upOeS-4Qy-1@gated-at.bofh.it>
In reply to#1732397
在 2017-09-14 23:51，Levin, Alexander (Sasha Levin) 写道：
> From: Icenowy Zheng <icenowy@aosc.xyz>
> 
> [ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ]

As DVFS for A33 doesn't exist in 4.9, this patch doesn't affect 4.9
at all.

> 
> The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
> be changeable by changing the rate of PLL_CPUX.
> 
> Add CLK_SET_RATE_PARENT flag to this clock.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
> b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
> index 9bd1f78a0547..d54e5db3959a 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
> @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, 
> "pll-ddr1",
>  static const char * const cpux_parents[] = { "osc32k", "osc24M",
>  					     "pll-cpux" , "pll-cpux" };
>  static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> -		     0x050, 16, 2, CLK_IS_CRITICAL);
> +		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
> 
>  static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);

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#1732682

From"Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com>
Date2017-09-15 04:20 +0200
Message-ID<upOox-4ZL-1@gated-at.bofh.it>
In reply to#1732677
On Fri, Sep 15, 2017 at 10:02:04AM +0800, icenowy@aosc.io wrote:
>在 2017-09-14 23:51，Levin, Alexander (Sasha Levin) 写道：
>>From: Icenowy Zheng <icenowy@aosc.xyz>
>>
>>[ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ]
>
>As DVFS for A33 doesn't exist in 4.9, this patch doesn't affect 4.9
>at all.

Dropped, thanks!

-- 

Thanks,
Sasha

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